ISL97686 查看數據表（PDF） - Renesas Electronics

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ISL97686

4-Channel LED Driver with Independent Channel Control for Dynamic Dimming

Renesas Electronics 

ISL97686

This is typically used in 3D systems to provide a higher current

level in 3D modes, but is not restricted to this application. CSEL

can be switched in operation and updates immediately in direct

PWM mode, and at the start of the next PWM dimming cycle in

other modes.

LED DC DIMMING

It is possible to control the LED current by applying a DC voltage

VDIM to the ISET1/2 pin via a resistor as in Figure 17.

ISET

VISET: 1.21V

RISET

RDIM

VDIM

FIGURE 17. LED CURRENT CONTROL WITH VDIM

If the VDIM is above VISET 1.21V, the brightness will reduce, and

vice versa. In this configuration, it is important that the control

voltage be set to the maximum brightness (minimum voltage)

level when the ISL97686 is enabled, even if the LEDs are not lit

at this point. This is necessary to allow the chip to calibrate to the

maximum current level that will need to be supported.

Otherwise, on-chip power dissipation will be higher at current

levels above the start-up level. Dimming with this technique

should be limited to a minimum of 10~20% brightness, as LED

current accuracy is increasingly degraded at lower levels.

PWM Dimming Frequency Adjustment

The dimming frequencies of serial interface and ACTL modes are

set by an external resistor at the PWM_SET pin, as shown in

Equation 3:

fPWM = --R-1---.-P-6--W-6----5-M-----S---1E---0-T--7-

(EQ. 3)

where fPWM is the desirable PWM dimming frequency and

RPWMSET is the setting resistor.

SPI INTERFACE

ISL97686 has an SPI interface for the daisy chain configuration

of a single controller and multiple LED drivers in Figure 18. The

master can control the particular channels of multiple LED

drivers with sharing 4 wires, SDI, SDO, CLK, and CS. Each

serialized dimming data can be encoded 10-bit resolution and

transferred to each driver ICs only at CS pin low period. The LED

driver will start particular channel dimming after loading the

dimming data when the CS level back to high.

SSPPI I

MAMSaTsEteRr

#1

SDI

SDO

CS CLK

#2

SDI

SDO

CS CLK

#3

SDI

SDO

CS

CLK

CS

SDI

(FIRST CHIP)

CH 1 CH 1 CH 1

MSB MSB-1 MSB-2

CH 4 CH 4 CH 4

LSB+2 LSB+1 LSB

CLK

SDO

(LAST CHIP)

CH 1 CH 1 CH 1

MSB MSB-1 MSB-2

CH 4 CH 4 CH 4

LSB+2 LSB+1 LSB

FIGURE 18. SPI INTERFACE AND CONTROL TIMING

DIMMING DATA LATCHED

FN7953 Rev.1.00

Sep 19, 2017

Page 10 of 22

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