ISL97686 查看數據表（PDF） - Renesas Electronics
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产品描述 (功能)
生产厂家
ISL97686
Renesas Electronics
ISL97686 Datasheet PDF : 22 Pages
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ISL97686
Pin Configurations
ISL97686
(28 LD 5x5 TQFN)
TOP VIEW
28 27 26 25 24 23 22
SDO 1
21 NC
CS 2
20 OSC
CLK 3
SDI 4
EXPOSED
THERMAL PAD
19 ISET2
18 ISET1
VLOGIC 5
17 COMP
EN_VSYNC 6
16 OVP
VDC 7
8
15 PWM_SET/PLL
9 10 11 12 13 14
CH2 1
CH1 2
PGND 3
CSEL 4
SDO 5
CS 6
CLK 7
SDI 8
VLOGIC 9
EN_VSYNC 10
VDC 11
VIN 12
EN 13
AGND 14
ISL97686
(28 LD SOIC)
TOP VIEW
28 CH3
27 CH4
26 PGND
25 NC
24 OSC
23 ISET2
22 ISET1
21 COMP
20 OVP
19 PWM_SET/PLL
18 PGND
17 CS
16 SLEW
15 GD
Pin Descriptions
TQFN SOIC PIN NAME PIN TYPE
PIN DESCRIPTION
15
SDO
I Serial data output to next driver
26
CS
I Chip select
37
CLK
I Serial clock
48
SDI
I Serial data input
59
VLOGIC
S Internal 2.5V Digital Bias Regulator. Needs Decoupling Capacitor added to ground
6 10 EN_VSYNC
I
Frame synchronization enable. Ties high to VDC for enable VSYNC function. PWM_SET/PLL also needs to be
configured with an RC network. Pin can be tied to VDC or VLOGIC to enable function
7 11
VDC
S Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor added to ground
8 12
VIN
S Main Power Input. Range: 9V to 32V
9 13
EN
I LED Driver Enable. Whole chip will shut down when low
10 14
AGND
S Analog Ground
11 15
GD
O External Boost FET gate control
12 16
SLEW
I Boost Regulation Switching Slew Rate control
13 17
CS
I External Boost FET current sense input
14 18
PGND
S Boost FET gate driver power ground and ground reference for CS pin
15 19 PWM_SET/PLL I For direct PWM mode, tie this pin high to VDC. For other non-VSYNC modes, connect to a resistor to set the
dimming frequency. If the VSYNC function is enabled, connect this pin to the PLL loop filter network.
16 20
OVP
I Overvoltage Protection Input as well as Output Voltage feedback pin
17 21
COMP
I Boost compensation
18 22
ISET1
I Resistor connection for setting LED current. 28.7kΩ= 100mA
FN7953 Rev.1.00
Sep 19, 2017
Page 3 of 22
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