M40Z300 查看數據表（PDF） - STMicroelectronics

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M40Z300

5 V or 3 V NVRAM supervisor for up to 8 LPSRAMs

STMicroelectronics 

Description

Figure 1. Logic diagram

VCC B +(1)

M40Z300, M40Z300W

THS

E

B

A

M40Z300

M40Z300W

VOUT

BL

E1CON

E2CON

E3CON

E4CON

RST

VSS B –(1)

1. For 16-pin SOIC package only.

Table 1. Signal names

THS

Threshold select input

E

Chip enable input

E1CON - E4CON

A, B

Conditioned chip enable output

Decoder inputs

RST

Reset output (open drain)

BL

Battery low output (open drain)

VOUT

VCC

VSS

B+

B–

Supply voltage output

Supply voltage

Ground

Positive battery pin

Negative battery pin(1)

NC

Not connected internally

1. For M40Z300W, B– must be connected to the negative battery terminal only (not to pin 8, VSS).

AI02242

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Doc ID 5679 Rev 5

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