M41T81M6F(2006) 查看數據表（PDF） - STMicroelectronics

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M41T81M6F
(Rev.:2006)

Serial access Real-Time Clock with alarm

STMicroelectronics 

Operation

M41T81

2.3

WRITE mode

In this mode the master transmitter transmits to the M41T81 slave receiver. Bus protocol is

shown in Figure 9 on page 12. Following the START condition and slave address, a logic '0'

(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”

will follow and is to be written to the on-chip address pointer. The data word to be written to

the memory is strobed in next and the internal address pointer is incremented to the next

address location on the reception of an acknowledge clock. The M41T81 slave receiver will

send an acknowledge clock to the master transmitter after it has received the slave address

see Figure 6 on page 11 and again after it has received the word address and each data

byte.

2.4

Data retention mode

With valid VCC applied, the M41T81 can be accessed as described above with READ or

WRITE Cycles. Should the supply voltage decay, the power input will be switched from the

VCC pin to the battery when VCC falls below the Battery Back-up Switchover Voltage (VSO).

At this time the clock registers will be maintained by the attached battery supply. On power-

up, when VCC returns to a nominal value, write protection continues for trec (see Figure 10

on page 23, Table 11 on page 24).

For a further, more detailed review of lifetime calculations, please see Application Note

AN1012.

Figure 9. WRITE mode sequence

BBUSUSACATICVTITIYV: ITY:

MMASATSETRER

SSDADALINLEINE S S

ADDWREOSRSDD(AAnT) A n DATA nDATA nD+A1TA n+1

BBUSUSACATICVTITIYV: ITY:

SLAVE

ADDRSESLSAVE

ADDRESS

DATA n+X DAPTA n+X P

AI00591

AI00895

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