M48Z128 查看數據表（PDF） - STMicroelectronics
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M48Z128 Datasheet PDF : 20 Pages
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Operating modes
M48Z128, M48Z128Y, M48Z128V
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
M48Z128/Y M48Z128/Y/V M48Z128/Y/V
–70
–85
–120
Unit
Min Max Min Max Min Max
tAVAV WRITE cycle time
70
85
tAVWL Address valid to WRITE enable Low
0
0
tAVEL Address valid to chip enable low
0
0
tWLWH WRITE enable pulse width
55
65
tELEH Chip enable low to chip enable high
55
75
tWHAX WRITE enable high to address transition
5
5
tEHAX Chip enable high to address transition
15
15
tDVWH Input valid to WRITE enable high
30
35
120
ns
0
ns
0
ns
85
ns
100
ns
5
ns
15
ns
45
ns
tDVEH Input valid to chip enable high
30
35
45
ns
tWHDX
tEHDX
tWLQZ(2)(3)
tAVWH
tAVEH
tWHQX(2)(3)
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
0
0
10
10
25
65
75
65
75
5
5
0
ns
10
ns
30
40 ns
100
ns
100
ns
5
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z128/Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all
inputs are treated as “Don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time tWP, write protection takes
place. When VCC drops below VSO, the control circuit switches power to the internal energy
source which preserves data.
The internal coin cell will maintain data in the M48Z128/Y/V after the initial application of
VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system
power returns and VCC rises above VSO, the battery is disconnected, and the power supply
is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to
allow for processor stabilization. After tER, normal RAM operation can resume.
For more information on battery storage life refer to the application note AN1012.
10/20
Doc ID 2426 Rev 5
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