M48Z128V-70PM1 查看數據表（PDF） - STMicroelectronics

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M48Z128V-70PM1

5.0 V or 3.3 V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM

STMicroelectronics 

M48Z128, M48Z128Y, M48Z128V

Operating modes

2.2

Note:

Note:

WRITE mode

The M48Z128/Y/V is in the WRITE mode whenever W and E are active. The start of a

WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated

by the earlier rising edge of W or E.

The addresses must be held valid throughout the cycle. E or W must return high for

minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE

cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX or

tEHDX afterward. G should be kept high during WRITE cycles to avoid bus contention;

although, if the output bus has been activated by a low on E and G, a low on W will disable

the outputs tWLQZ after W falls.

Figure 6. WRITE enable controlled, WRITE AC waveforms

A0-A16

E

W

DQ0-DQ7

tAVEL

tAVAV

VALID

tAVWH

tAVWL

tWLWH

tWLQZ

tWHDX

DATA INPUT

tDVWH

Output enable (G) = high.

tWHAX

tWHQX

AI01198

Figure 7.

A0-A16

E

Chip enable controlled, WRITE AC waveforms

tAVAV

VALID

tAVEH

tAVEL

tELEH

tAVWL

tEHAX

W

tEHDX

DQ0-DQ7

DATA INPUT

tDVEH

Output enable (G) = high.

AI01199

Doc ID 2426 Rev 5

9/20

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