M48T59Y-70PC1E 查看數據表（PDF） - STMicroelectronics
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M48T59Y-70PC1E Datasheet PDF : 29 Pages
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M48T59, M48T59Y, M48T59V*
Data Retention Mode
With valid VCC applied, the M48T59/Y/V operates
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T59/Y/V may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T59/Y/V for
an accumulated period of at least 7 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the battery is discon-
nected and the power supply is switched to exter-
nal VCC. Deselect continues for trec after VCC
reaches VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
10/29
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