M48T59 查看數據表（PDF） - STMicroelectronics

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M48T59

5.0 or 3.3V, 64 Kbit (8 Kbit x8) TIMEKEEPER® SRAM

STMicroelectronics 

M48T59, M48T59Y, M48T59V*

WRITE Mode

The M48T59/Y/V is in the WRITE Mode whenever

W and E are low. The start of a WRITE is refer-

enced from the latter occurring falling edge of W or

E. A WRITE is terminated by the earlier rising

edge of W or E. The addresses must be held valid

throughout the cycle. E or W must return high for

a minimum of tEHAX from Chip Enable or tWHAX

from WRITE Enable prior to the initiation of anoth-

er READ or WRITE cycle. Data-in must be valid

tDVWH prior to the end of WRITE and remain valid

for tWHDX afterward. G should be kept high during

WRITE cycles to avoid bus contention; however, if

the output bus has been activated by a low on E

and G a low on W will disable the outputs tWLQZ af-

ter W falls.

Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveforms

A0-A12

E

W

DQ0-DQ7

tAVEL

tAVAV

VALID

tAVWH

tWHAX

tAVWL

tWLWH

tWLQZ

tWHDX

DATA INPUT

tDVWH

tWHQX

AI01386

Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms

A0-A12

E

tAVEL

tAVWL

tAVAV

VALID

tAVEH

tELEH

tEHAX

W

tEHDX

DQ0-DQ7

DATA INPUT

tDVEH

AI01387B

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