M48T02-70PC1 查看數據表（PDF） - STMicroelectronics

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M48T02-70PC1

5.0V, 16 Kbit (2Kb x 8) TIMEKEEPER® SRAM

STMicroelectronics 

M48T02, M48T12

WRITE Mode

The M48T02/12 is in the WRITE Mode whenever

W and E are active. The start of a WRITE is refer-

enced from the latter occurring falling edge of W or

E. A WRITE is terminated by the earlier rising

edge of W or E. The addresses must be held valid

throughout the cycle. E or W must return high for

a minimum of tEHAX from Chip Enable or tWHAX

from WRITE Enable prior to the initiation of anoth-

er READ or WRITE cycle. Data-in must be valid tD-

VWH prior to the end of WRITE and remain valid for

tWHDX afterward. G should be kept high during

WRITE cycles to avoid bus contention; although, if

the output bus has been activated by a low on E

and G, a low on W will disable the outputs tWLQZ

after W falls.

Figure 7. WRITE Enable Controlled, WRITE AC Waveform

A0-A10

E

tAVEL

tAVWL

tAVAV

VALID

tAVWH

tWLWH

W

DQ0-DQ7

tWLQZ

tWHDX

DATA INPUT

tDVWH

tWHAX

tWHQX

AI01331

Figure 8. Chip Enable Controlled, WRITE AC Waveforms

A0-A10

E

tAVEL

tAVWL

tAVAV

VALID

tAVEH

tELEH

tEHAX

W

tEHDX

DQ0-DQ7

DATA INPUT

tDVEH

AI01332B

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