DS1994L-F5 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1994L-F5

4kb Plus Time Memory iButton

Dallas Semiconductor -> Maxim Integrated 

DS1994

Skip ROM [CCh]

This command can save time in a single drop bus system by allowing the bus master to access the

memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus

and a read command is issued following the Skip ROM command, data collision occurs on the bus as

multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result).

Search ROM [F0h]

When a system is initially brought up, the bus master might not know the number of devices on the 1-

Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process

of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process

is the repetition of a simple three–step routine: read a bit, read the complement of the bit, then write the

desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM.

After one complete pass, the bus master knows the contents of the ROM in one device. Additional passes

can identify the remaining number of devices and their ROM codes. See Chapter 5 of the Book of

DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual

example.

Search Interrupt [ECh]

This ROM command works exactly as the normal ROM Search, but it identifies only devices with

interrupts that have not yet been acknowledged.

1-WIRE SIGNALING

The DS1994 requires strict protocols to ensure data integrity. The protocol consists of five types of

signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, read data, and

interrupt pulse. The bus master initiates all these signals except presence pulse and interrupt pulse. The

initialization sequence required to begin any communication with the DS1994 is shown in Figure 10. A

reset pulse followed by a presence pulse indicates the DS1994 is ready to send or receive data given the

correct ROM command and memory function command. The bus master transmits (Tx) a reset pulse

(tRSTL, minimum 480ms). The bus master then releases the line and goes into receive mode (Rx). The 1-

Wire bus is pulled to a high state through the pullup resistor. After detecting the rising edge on the data

line, the DS1994 waits (tPDH, 15ms to 60ms) and then transmits the presence pulse (tPDL, 60ms to 240ms).

There are special conditions if interrupts are enabled for which the bus master must check the state of the

1-Wire bus after being in the Rx mode for 480ms. These conditions are discussed in the Interrupt section.

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated in Figure 11. The master driving the data line

low initiates all time slots. The falling edge of the data line synchronizes the DS1994 to the master by

triggering a delay circuit in the DS1994. During write time slots, the delay circuit determines when the

DS1994 samples the data line. For a read data time slot, if a 0 is to be transmitted, the delay circuit

determines how long the DS1994 holds the data line low overriding the 1 generated by the master. If the

data bit is a 1, the iButton leaves the read data time slot unchanged.

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