MAS17502FS 查看數據表（PDF） - Dynex Semiconductor
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MAS17502FS Datasheet PDF : 30 Pages
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MA17502
Cycles*
Operation
Op Code/Ext Mnemonic
Format
M
P
B
COMPARE
Single-Precision Compare
F1
3X
4X C
F2
F3
F0
4A A
CR
CB
CBX
CISP
CISN
C
CIM
R
B
BX
ISP
ISN
D,DX
IM
1
0
0
2
1
0
2
1
0
1
0
0
1
0
0
3
0
0
2
0
0
Compare Between Limits
F4
CBL
D,DX
4
2.75 1.75a
Double-Precision Compare
F7
F6
DCR
DC
R
D,DX
1
2
0
4
0
0
JUMP/BRANCH
Jump on Condition
70
JC
D,DX
2
0.5
1a
71
JCl
I,IX
3
0.5
1a
Jump to Subroutine
72
Subtract One and Jump
73
Branch Unconditionally
74
Branch if Equal to (zero)
75
Branch if Less than (zero)
76
Branch to Executive
77
Branch if Less than or Equal to (Zero)
78
Branch if Greater than (Zero)
79
Branch if Not Equal to (Zero)
7A
Branch if Greater than or Equal to (Zero) 7B
JS
SOJ
BR
BEz
BLT
BEX
BLE
BGT
BNZ
BGE
D,DX
D,DX
ICR
ICR
ICR
S
ICR
ICR
ICR
ICR
2
2
0
2
2.5
1a
2
2
0
1.5
1
1a
1.5
1
1a
16
12
3a
1.5
1
1a
1.5
1
1a
1.5
1
1a
1.5
1
1a
SHIFT
Shift Left Logical
60
Shift Right Logical
61
Shift Right Arithmetic
62
Shift Left Cyclic
63
Double Shift Left Logical
65
Double Shift Right Logical
66
Double Shift Right Arithmetic
67
Double Shift Left Cyclic
68
Shift Logical, Count in Register
6A
Shift Arithmetic, Count in Register 6B
Shift Cyclic, Count in Register
6C
Double Shift Logical, Count in Register
6D
Double Shift Arithmetic, Count in Register 6E
Double Shift Cyclic, Count in Register
6F
SLL
R
SRL
R
SRA
R
SLC
R
DSLL
R
DSRL
R
DSRA
R
DSLC
R
SLR
R
SAR
R
SCR
R
DSLR
R
DSAR
R
DSCR
R
1
1
0
1
1
0
1
1
0
1
1
0
1
3
0
1
2
0
1
2
0
1
3
0
1
1
3
1
1.5
3.50a
1
1
3.25a
1
2.25
4a
1
3.19 4.94a
1
3.5
3a
* M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles), a = average if more than one alternative exists.
Table 6a (continued): Instruction Summary
16/30
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