74HC125 查看數據表（PDF） - ON Semiconductor

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74HC125

Quad 3−State Noninverting Buffers

ON Semiconductor 

74HC125

Quad 3−State Noninverting

Buffers

High−Performance Silicon−Gate CMOS

The 74HC125 is identical in pinout to the LS125. The device inputs

are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

The HC125 noninverting buffer is designed to be used with 3−state

memory address drivers, clock drivers, and other bus−oriented

systems. The device has four separate output enables that are

active−low.

Features

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the JEDEC Standard No. 7A Requirements

• ESD Performance: HBM > 2000 V; Machine Model > 200 V

• Chip Complexity: 72 FETs or 18 Equivalent Gates

• These are Pb−Free Devices

http://onsemi.com

MARKING

DIAGRAMS

14

1

14

SOIC−14

D SUFFIX

CASE 751A

1

HC125G

AWLYWW

14

1

TSSOP−14

DT SUFFIX

CASE 948G

14

HC

125

ALYWG

G

1

A

L, WL

Y

W, WW

G or G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

© Semiconductor Components Industries, LLC, 2007

1

March, 2007 − Rev. 0

Publication Order Number:

74HC125/D

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