IR3Y48 查看數據表（PDF） - Sharp Electronics

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IR3Y48

CCD Signal Process & Digital Interface IC

Sharp Electronics 

A/D Converter Circuit

IR3Y48M integrates 20 MHz 10-bit full pipeline A/D

converter (ADC).

A/D CONVERSION RANGE

The analog input range of the ADC is determined

by VREF circuit integrated in IR3Y48M. At ADC

direct input (ADIN) mode (Mode (1) Register D5 =

1), feed 1 Vp-p (full scale) signal based on clamp

level as zero reference into ADIN input pin.

A/D CONVERTER OUTPUT CODE

(AT MODE (1) REGISTER D5 = 1)

The digital output format is binary.

Thus, "all zero" digital output with zero reference

input (ADIN = CLPCAP), "all one" digital output with

full-scale input (ADIN = CLPCAP + 1 V (TYP.)).

CLOCK, PIPELINE DELAY AND OUTPUT DIGITAL

DATA TIMING

The A/D conversion is performed based on the

clock fed to ADCK pin.

The track-and-hold operation is completed at falling

(when not inverted) edge of ADCK.

The 10-bit width parallel data is obtained at rising

edge after 5.5 clock pipeline delay. (Sampling edge

is selectable by register setting.)

CODE AT CLAMP LEVEL

(AT MODE (1) REGISTER D5 = 0, D4 = 1)

The output code at clamp level can be set

throughout (1 to) 16 to 127 LSB at the step of 1

LSB by register setting.

IR3Y48M

ADC OUTPUT CODE LOGIC

ADC digital output is High-Z under following

conditions :

q Set ADC output register to 1

w Set SYBYN pin low

e Power down (by STBYN or register control)

DIGITAL OUTPUT CODE

According to ADIN, digital codes are determined as

follows :

Data Output at Straight Binary

[Mode (1) Register D2 = 0, D5 = 1]

ADIN

DIGITAL CODE

MSB

LSB

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Clamp

reference + 1 V

1

1

1

1

1

1

1

1

1

1

:

:

:

1000000000

:

0111111111

:

Clamp

reference

:

0000000000

11

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