Preliminary W77E468
Examples of Timed Assessing are shown below.
Example 1: Valid access
MOV TA, #0AAh 3 M/C
MOV TA, #055h 3 M/C
MOV WDCON, #00h 3 M/C
Note: M/C = Machine Cycles
Example 2: Valid access
MOV TA, #0AAh
MOV TA, #055h
NOP
SETB EWT
3 M/C
3 M/C
1 M/C
2 M/C
Example 3: Invalid access
MOV TA, #0AAh
MOV TA, #055h
NOP
NOP
CLR POR
3 M/C
3 M/C
1 M/C
1 M/C
2 M/C
Example 4: Invalid Access
MOV TA, #0AAh 3 M/C
NOP
1 M/C
MOV TA, #055h 3 M/C
SETB EWT
2 M/C
In the first two examples, the writing to the protected bits is done before the 3 machine cycle window
closes. In Example 3, however, the writing to the protected bit occurs after the window has closed,
and so there is effectively no change in the status of the protected bit. In Example 4, the second write
to TA occurs 4 machine cycles after the first write, therefore the timed access window in not opened
at all, and the write to the protected bit fails.
ON-CHIP MTP ROM CHARACTERISTICS
The W77E468 has several modes to program the on-chip MTP ROM. All these operations are
configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),
OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and VPP( EA ). Moreover, the A15−A0(P2.7−P2.0,
P1.7−P1.0) and the D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these
operations.
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