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AN4506

L3GD20H: 3-axis digital output gyroscope

STMicroelectronics 

First-in first-out (FIFO) buffer

AN4506

6.3

6.3.1

6.3.2

FIFO modes

The L3GD20H FIFO buffer can be configured to operate in five different modes selectable

by the FM[2:0] field in the FIFO_CTRL register. Available configurations ensure a high level

of flexibility and extend the number of functions usable in application development.

Bypass, FIFO, Stream, Dynamic Stream, Stream-to-FIFO, Bypass-to-Stream and Bypass-

to-FIFO modes are described in the following paragraphs.

Bypass mode

When Bypass mode is enabled, FIFO is not operational: buffer content is cleared, output

registers (0x28 to 0x2D) are frozen at the last value loaded, and the FIFO buffer remains

empty until another mode is selected.

Follow these steps for Bypass mode configuration:

1. Turn on FIFO by setting the FIFO_En bit to “1” in control register 5 (0x24). After this

operation the FIFO buffer is enabled but isn’t collecting data, output registers are

frozen to the last sample set loaded.

2. Activate Bypass mode by setting the FM[2:0] field to “000” in the FIFO_CTRL register

(0x2E). If this mode is enabled, the FIFO_SRC register (0x2F) is forced equal to 0x20.

Bypass mode must be used in order to stop and reset the FIFO buffer when a different

mode is operating. Note that setting the FIFO buffer in Bypass mode clears the whole buffer

content.

FIFO mode

In FIFO mode, the buffer continues filling until full (32 sample sets stored,) then it stops

collecting data and the FIFO content remains unchanged until a different mode is selected.

Follow these steps for FIFO mode configuration:

1. Turn on FIFO by setting the FIFO_En bit to “1” in control register 5 (0x24). After this

operation the FIFO buffer is enabled but is not collecting data, output registers are

frozen to the last samples set loaded.

2. Activate FIFO mode by setting the FM[2:0] field to “001” in the FIFO control register

(0x2E).

By selecting this mode, FIFO starts data collection and the source register (0x2F) changes

according to the number of samples stored. At the end of the procedure, the FIFO source

register is set to 0xDF and the OVRN flag generates an interrupt if the INT2_ORun bit is set

to 1 in the CTRL3 register. Data can be retrieved when the OVRN is “1”, by performing a 32

sample set read from the output registers. Data can also be retrieved on the FTH flag

instead of the OVRN when the application requires a lower number of samples.

Communication speed is not so important in FIFO mode because data collection is stopped

and there is no risk of overwriting data already acquired. Before restarting FIFO mode, at

the end of the reading procedure, it is necessary to set Bypass mode (to clear the FIFO

content).

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