R4F2112R 查看數據表（PDF） - Renesas Electronics
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R4F2112R Datasheet PDF : 984 Pages
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2.7.8 Memory Indirect@@aa:8 ................................................................................... 57
2.7.9 Effective Address Calculation ................................................................................ 58
2.8 Processing States.................................................................................................................. 60
2.9 Usage Note........................................................................................................................... 62
2.9.1 TAS Instruction ...................................................................................................... 62
2.9.2 STM/LDM Instruction............................................................................................ 62
2.9.3 Notes on Using the Bit Operation Instruction......................................................... 62
2.9.4 EEPMOV Instruction.............................................................................................. 63
Section 3 MCU Operating Modes .......................................................................65
3.1 Operating Mode Selection ................................................................................................... 65
3.2 Register Descriptions ........................................................................................................... 66
3.2.1 Mode Control Register (MDCR) ............................................................................ 66
3.2.2 System Control Register (SYSCR)......................................................................... 67
3.2.3 Serial Timer Control Register (STCR) ................................................................... 69
3.2.4 System Control Register 3 (SYSCR3) .................................................................... 71
3.2.5 Port Control Register 2 (PTCNT2) ......................................................................... 72
3.3 Operating Mode Descriptions .............................................................................................. 73
3.3.1 Mode 2.................................................................................................................... 73
3.4 Address Map ........................................................................................................................ 73
Section 4 Resets...................................................................................................75
4.1 Types of Resets.................................................................................................................... 75
4.2 Input/Output Pin .................................................................................................................. 76
4.3 Register Descriptions ........................................................................................................... 77
4.3.1 Reset Status Register (RSTSR)............................................................................... 77
4.3.2 System Control Register (SYSCR)......................................................................... 78
4.3.3 Timer Control/Status Register (TCSR)................................................................... 80
4.4 Pin Reset .............................................................................................................................. 83
4.5 Power-on Reset .................................................................................................................... 84
4.6 Watchdog Timer Reset ........................................................................................................ 85
4.7 Determination of Reset Generation Source.......................................................................... 85
Section 5 Exception Handling .............................................................................87
5.1 Exception Handling Types and Priority............................................................................... 87
5.2 Exception Sources and Exception Vector Table .................................................................. 88
5.3 Reset .................................................................................................................................... 91
5.3.1 Reset Exception Handling ...................................................................................... 91
5.3.2 Interrupts Immediately after Reset.......................................................................... 92
5.3.3 On-Chip Peripheral Modules after Reset is Cancelled ........................................... 92
Rev. 1.00 May 09, 2008 Page x of xxvi
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