MB90350E 查看數據表（PDF） - Cypress Semiconductor
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MB90350E Datasheet PDF : 85 Pages
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MB90350E Series
1. Product Lineup1 (Without Clock supervisor function)
■ Flash memory products
Part Number
Parameter
MB90F351E
MB90F352E
MB90F351TE
MB90F352TE
MB90F351ES
MB90F352ES
MB90F351TES
MB90F352TES
Type
CPU
Flash memory products
F2MC-16LX CPU
System clock
PLL clock multiplication circuit ( 1, 2, 3, 4, 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL 6)
ROM
64 Kbytes Flash memory : MB90F351E(S), MB90F351TE(S)
128 Kbytes Dual operation Flash memory (Erase/write and read can be operated at the same time) :
MB90F352E(S), MB90F352TE(S)
RAM
4 Kbytes
Emulator-specific power
supply*
Sub clock pin
(X0A, X1A)
Yes
No
(Max 100 kHz)
Clock supervisor
No
Low voltage/CPU
operation detection
No
Yes
No
Yes
reset
Operating voltage
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter/Flash programming
4.5 V to 5.5 V : at using external bus
Operating
temperature
40C to 125C
Package
LQFP-64
2 channels
LIN-UART
I2C (400 kbps)
Wide range of baud rate settings using a dedicated baud rate generator (reload timer)
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
1 channel
A/D converter
16-bit reload timer
(2 channels)
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
16-bit Free-run timer
(2 channels)
Free-run Timer 0 (clock input FRCK0) corresponds to ICU0/1.
Free-run Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU4/5/6/7.
Signals an interrupt when overflowing.
Supports Timer
Operation clock
Clear when
frequency :
iftsmysa, tfcshyess/2O1,uftspyust/2C2o, mfspyasr/2e3(,cfhs.y0s,/2ch4,.4fs)y.s/25,
fsys/26,
fsys/27
(fsys Machine clock frequency)
16-bit output
compare
4 channels
Signals an interrupt when 16-bit free-run Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
(Continued)
Document Number: 002-04493 Rev. *A
Page 4 of 84
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