UPSD3212A 查看數據表（PDF） - STMicroelectronics

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UPSD3212A

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

uPSD3212A, uPSD3212C, uPSD3212CV

USART Interrupt

– The USART Interrupt is generated by RI

(Receive Interrupt) OR TI (Transmit Interrupt).

– When the USART Interrupt is generated, the

corresponding request flag must be cleared by

the software. The interrupt service routine will

have to check the various USART registers to

determine the source and clear the

corresponding flag.

– Both USART’s are identical, except for the

additional interrupt controls in the Bit 4 of the

additional interrupt control registers (A7H,

B7H).

Interrupt Priority Structure

Each interrupt source can be assigned one of two

priority levels. Interrupt priority levels are defined

by the interrupt priority special function register IP

and IPA.

0 = low priority

1 = high priority

A low priority interrupt may be interrupted by a

high priority interrupt level interrupt. A high priority

interrupt routine cannot be interrupted by any oth-

er interrupt source. If two interrupts of different pri-

ority occur simultaneously, the high priority level

request is serviced. If requests of the same priority

are received simultaneously, an internal polling

sequence determines which request is serviced.

Thus, within each priority level, there is a second

priority structure determined by the polling se-

quence.

Interrupts Enable Structure

Each interrupt source can be individually enabled

or disabled by setting or clearing a bit in the inter-

rupt enable special function register IE and IEA. All

interrupt source can also be globally disabled by

the clearing Bit EA in IE (see Table 19). Please

see Tables 20, 21, 22, and 23 for individual bit de-

scriptions.

Table 18. Priority Levels

Source

Int0

2nd USART

Timer 0

I²C

Int1

reserved

Timer 1

USB

1st USART

Timer 2+EXF2

Priority with Level

0 (highest)

1

2

3

4

5

6

7

8

9 (lowest)

Table 19. SFR Register

SFR Reg

Addr Name

7

6

A7 IEA

—

—

A8

IE

EA

—

B7 IPA

—

—

B8

IP

—

—

Bit Register Name

5

4

3

2

—

ES2

—

—

ET2

ES

ET1 EX1

—

PS2

—

—

PT2

PS

PT1 PX1

1

EI2C

ET0

PI2C

PT0

0

Reset

Value

Comments

EUSB

00

Interrupt

Enable (2nd)

EX0

00

Interrupt

Enable

PUSB

00

Interrupt

Priority (2nd)

PX0

00

Interrupt

Priority

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