AD5247 查看數據表（PDF） - Analog Devices

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AD5247

128-Position I2C Compatible Digital Potentiometer

Analog Devices 

AD5247

I2C INTERFACE

Table 5. Write Mode

S0

1 0 1 1 1 0 WA X

Slave Address Byte

D6 D5 D4 D3 D2 D1 D0 A P

Data Byte

Table 6. Read Mode

S0

1 0 1 1 1 0 R A0

Slave Address Byte

D6 D5 D4 D3 D2 D1 D0 A P

Data Byte

S = Start Condition.

P = Stop Condition.

A = Acknowledge.

X = Don’t Care.

W = Write.

R = Read.

D6, D5, D4, D3, D2, D1, D0 = Data Bits.

SCL

t2

SDA

t1

P

S

t8

t9

t6

t3

t4

t7

t9

t8

t2

t5

S

Figure 31. I2C Interface, Detailed Timing Diagram

t10

P

1

SCL

SDA

0

1

0

11 1

START BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

9

1

9

1

0 R/W

X D6 D5 D4 D3 D2 D1 D0

ACK BY

AD5247

FRAME 2

DATA BYTE

ACK BY

AD5247

STOP BY

MASTER

Figure 32. Writing to the RDAC Register

SCL

SDA

START BY

MASTER

1

9

1

01

0

11 1

0 R/W

0

FRAME 1

SLAVE ADDRESS BYTE

ACK BY

AD5247

9

D6 D5 D4 D3 D2 D1 D0

FRAME 2

RDAC REGISTER

NO ACK

BY MASTER

STOP BY

MASTER

Figure 33. Reading from the RDAC Register

Rev. 0 | Page 12 of 20

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