AD5247BKS50-RL7 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD5247BKS50-RL7 Datasheet PDF : 20 Pages
| |||
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a
new component may be optimized at another. When two
systems operate the same signal at two different voltages, proper
level shifting is needed. For instance, one can use a 3.3 V
E2PROM to interface with a 5 V digital potentiometer. A level
shifting scheme is needed to enable a bidirectional communi-
cation so that the setting of the digital potentiometer can be
stored to and retrieved from the E2PROM. Figure 35 shows one
of the implementations. M1 and M2 can be any N channel
signal FETs, or if VDD falls below 2.5 V, M1 and M2 can be low
threshold FETs such as the FDV301N.
VDD1 = 3.3V
RP
SDA1
SCL1
3.3V
RP
RP
G
S
D
G
M1
S
D
M2
VDD2 = 5V
RP
SDA2
SCL2
5V
E2PROM
AD5247
Figure 35. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 36 and Figure 37.
This applies to the digital input pins SDA and SCL.
340Ω
LOGIC
GND
Figure 36. ESD Protection of Digital Pins
A,W
GND
Figure 37. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5247 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A and W that
exceed VDD or GND will be clamped by the internal forward
biased diodes (see Figure 38).
AD5247
VDD
A
W
GND
Figure 38. Maximum Terminal Voltages Set by VDD and GND
MAXIMUM OPERATING CURRENT
At low code values, the user should be aware that due to low
resistance values, the current through the RDAC may exceed
the 5 mA limit. In Figure 39, a 5 V supply is placed on the wiper,
and the current through terminals W and B is plotted with
respect to code. A line is also drawn denoting the 5 mA current
limit. Note that at low code values (particularly for the 5 kΩ and
10 kΩ options), the current level increases significantly. Care
should be taken to limit the current flow between W and B in
this state to a maximum continuous current of 5 mA and a
maximum pulse current of no more than 20 mA. Otherwise,
degradation or possible destruction of the internal switch
contacts can occur.
100.00
10.00
1.00
0.10
0.01
0
5mA CURRENT LIMIT
RAB = 5kΩ
RAB = 10kΩ
RAB = 50kΩ
RAB = 100kΩ
16
32
48
64
80
96 112 128
CODE (Decimal)
Figure 39. Maximum Operating Current
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
terminals A and W (see Figure 38), it is important to power
VDD/GND before applying any voltage to terminals A and W;
otherwise, the diode will be forward biased such that VDD will be
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA/VW. The relative order of
powering VA and VW and the digital inputs is not important as
long as they are powered after VDD/GND.
Rev. 0 | Page 15 of 20
Share Link: 