STK15C68(2011) 查看數據表（PDF） - Cypress Semiconductor
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STK15C68 Datasheet PDF : 17 Pages
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STK15C88
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [11, 12]
Parameter
Alt
Description
25 ns
Min
Max
45 ns
Unit
Min Max
tRC
tAVAV
STORE/RECALL Initiation Cycle Time
25
45
ns
tSA[11]
tAVEL
Address Setup Time
0
0
ns
tCW[11]
ly. tHACE[7, 11]
n tRECALL
tELEH
tELAX
Clock Pulse Width
Address Hold Time
RECALL Duration
20
30
20
20
20
20
s o Switching Waveforms
am Figure 10. CE Controlled Software STORE/RECALL Cycle [12]
n progr ADDRESS
ns. ductio CE
desiging pro OE
tRC
ADDRESS # 1
tSA
tSCE
tHACE
tRC
ADDRESS # 6
NoItnrepcroodmumcteionndetod sfourpnpeowrt ongo DQ (DATA)
DATA VALID
t / t STORE RECALL
HIGH IMPEDANCE
DATA VALID
ns
ns
s
Notes
11. The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence).
12. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Document Number: 001-50593 Rev. *C
Page 12 of 17
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