STK15C68(2011) 查看數據表（PDF） - Cypress Semiconductor
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STK15C68 Datasheet PDF : 17 Pages
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STK15C88
Pin Configurations
Figure 1. Pin Diagram - 28-pin SOIC
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r new odnegsoiginngs prod Table 1. Pin Definitions - 28-pin SOIC
fo rt Pin Name Alt
I/O Type
Description
d po A0–A14
nde sup DQ0-DQ7
Input
Input or
Output
Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Bidirectional Data I/O lines. Used as input or output lines depending on operation.
me to WE
W
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the
I/O pins is written to the specific address location.
com tion CE
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
t re duc OE
G
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
No pro VSS
Ground Ground for the Device. The device is connected to ground of the system.
In VCC
Power Supply Power Supply Inputs to the Device.
Document Number: 001-50593 Rev. *C
Page 3 of 17
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