LP62S4096EU-55LLIF 查看數據表（PDF） - AMIC Technology

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LP62S4096EU-55LLIF

512K X 8 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

Package Information

36LD CSP (6 x 8 mm) Outline Dimensions

TOP VIEW

Ball*A1 CORNER

123456

A

B

C

D

E

F

G

H

SIDE VIEW

LP62S4096E-I Series

unit: mm

BOTTOM VIEW

Ball#A1 CORNER

0.10 S C

0.25 S C A B

b (36X)

654321

A

B

C

D

E

F

G

H

B

e

D1

A

D

0.20(4X)

C SEATING PLANE

Dimensions in mm

Symbol

MIN. NOM. MAX.

A

1.00 1.10 1.20

A1

0.16 0.21 0.26

A2

0.48 0.53 0.58

D

5.80 6.00 6.20

E

7.80 8.00 8.20

D1

--- 3.75 ---

E1

--- 5.25 ---

e

--- 0.75 ---

b

0.25 0.30 0.35

Note:

1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS

ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).

2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS

OF THE SOLDER BALLS.

3. DIMENSION b IS MEASURED AT THE MAXIMUM.

THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE

SOLDER BALL AND THE BODY EDGE.

4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.25mm (SMD)

SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.25mm (NSMD)

(May, 2010, Version 3.3)

12

AMIC Technology, Corp.

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