KSZ9031MNX 查看數據表（PDF） - Microsemi Corporation

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KSZ9031MNX

Gigabit Ethernet Transceiver with GMII/MII Support

Microsemi Corporation 

KSZ9031MNX

After auto-negotiation is completed, the link status is updated in Register 1h, Bit [2], and the link partner capabilities are

updated in Registers 5h, 6h, and Ah.

The auto-negotiation finite state machines use interval timers to manage the auto-negotiation process. The duration of

these timers under normal operating conditions is summarized in Table 3-2.

TABLE 3-2: AUTO-NEGOTIATION TIMERS

Auto-Negotiation Interval Timers

Transmit Burst Interval

Transmit Pulse Interval

FLP Detect Minimum Time

FLP Detect Maximum Time

Receive Minimum Burst Interval

Receive Maximum Burst Interval

Data Detect Minimum Interval

Data Detect Maximum Interval

NLP Test Minimum Interval

NLP Test Maximum Interval

Link Loss Time

Break Link Time

Parallel Detection Wait Time

Link Enable Wait Time

Time Duration

16 ms

68 µs

17.2 µs

185 µs

6.8 ms

112 ms

35.4 µs

95 µs

4.5 ms

30 ms

52 ms

1480 ms

830 ms

1000 ms

3.8 10/100 Mbps Speeds Only

Some applications require link-up to be limited to 10/100 Mbps speeds only.

After power-up/reset, the KSZ9031MNX can be restricted to auto-negotiate and link-up to 10/100 Mbps speeds only by

programming the following register settings:

1. Set Register 0h, Bit [6] = ‘0’ to remove 1000 Mbps speed.

2. Set Register 9h, Bits [9:8] = ‘00’ to remove Auto-Negotiation advertisements for 1000 Mbps full/half duplex.

3. Write a ‘1’ to Register 0h, Bit [9], a self-clearing bit, to force a restart of Auto-Negotiation.

Auto-Negotiation and 10BASE-T/100BASE-TX speeds use only differential pairs A (pins 2, 3) and B (pins 7, 8). Differ-

ential pairs C (pins 10, 11) and D (pins 14, 15) can be left as no connects.

3.9 GMII Interface

The Gigabit Media Independent Interface (GMII) is compliant to the IEEE 802.3 Specification. It provides a common

interface between GMII PHYs and MACs, and has the following key characteristics:

• Pin count is 24 pins (11 pins for data transmission, 11 pins for data reception, and 2 pins for carrier and collision

indication).

• 1000 Mbps is supported at both half- and full-duplex.

• Data transmission and reception are independent and belong to separate signal groups.

• Transmit data and receive data are each 8 bits wide, a byte.

In GMII operation, the GMII pins function as follows:

• The MAC sources the transmit reference clock, GTX_CLK, at 125 MHz for 1000 Mbps.

• The PHY recovers and sources the receive reference clock, RX_CLK, at 125 MHz for 1000 Mbps.

• TX_EN, TXD[7:0], and TX_ER are sampled by the KSZ9031MNX on the rising edge of GTX_CLK.

• RX_DV, RXD[7:0], and RX_ER are sampled by the MAC on the rising edge of RX_CLK.

• CRS and COL are driven by the KSZ9031MNX and do not have to transition synchronously with respect to either

GTX_CLK or RX_CLK.

DS00002096C-page 18

 2016 Microchip Technology Inc.

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