W83977ATG 查看數據表（PDF） - Winbond
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W83977ATG Datasheet PDF : 198 Pages
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W83977ATF/W83977ATG
7.7.6 Set5.Reg6, 7 - Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number
(LST_NU)..........................................................................................................................................72
7.8 Set6 - IR Physical Layer Control Registers......................................................................... 72
7.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2).........................................................72
7.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width............................................................73
7.8.3 Set6.Reg2 - SIR Pulse Width ...............................................................................................74
7.8.4 Set6.Reg3 - Set Select Register...........................................................................................74
7.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU) ...............................74
7.9 Set7 - Remote control and IR module selection registers................................................... 75
7.9.1 4.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC) ........................................75
7.9.2 Set7.Reg1 - Remote Infrared Transmitter Control (RIR_TXC) .............................................77
7.9.3 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG)...................................................78
7.9.4 Set7.Reg3 - Sets Select Register (SSR) ..............................................................................79
7.9.5 Set7.Reg4 - Infrared Module (Front End) Select 1 (IRM_SL1) .............................................80
7.9.6 Set7.Reg5 - Infrared Module (Front End) Select 2 (IRM_SL2) .............................................80
7.9.7 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3) .............................................81
7.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR) ....................................................81
8. PARALLEL PORT.......................................................................................................................... 83
8.1 Printer Interface Logic ......................................................................................................... 83
8.2 Enhanced Parallel Port (EPP) ............................................................................................. 84
8.2.1 Data Swapper.......................................................................................................................85
8.2.2 Printer Status Buffer .............................................................................................................85
8.2.3 Printer Control Latch and Printer Control Swapper...............................................................86
8.2.4 EPP Address Port ................................................................................................................86
8.2.5 EPP Data Port 0-3 ................................................................................................................87
8.2.6 Bit Map of Parallel Port and EPP Registers..........................................................................87
8.2.7 EPP Pin Descriptions ...........................................................................................................88
8.2.8 EPP Operation .....................................................................................................................88
8.3 Extended Capabilities Parallel (ECP) Port .......................................................................... 89
8.3.1 ECP Register and Mode Definitions .....................................................................................89
8.3.2 Data and ecpAFifo Port ........................................................................................................90
8.3.3 Device Status Register (DSR) ..............................................................................................90
8.3.4 Device Control Register (DCR).............................................................................................91
8.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 .........................................................................91
8.3.6 ecpDFifo (ECP Data FIFO) Mode = 011...............................................................................92
8.3.7 tFifo (Test FIFO Mode) Mode = 110 .....................................................................................92
8.3.8 cnfgA (Configuration Register A) Mode = 111 ......................................................................92
8.3.9 cnfgB (Configuration Register B) Mode = 111 ......................................................................92
8.3.10 ecr (Extended Control Register) Mode = all..........................................................................93
8.3.11 Bit Map of ECP Port Registers .............................................................................................94
8.3.12 ECP Pin Descriptions ...........................................................................................................95
8.3.13 ECP Operation .....................................................................................................................96
8.3.14 FIFO Operation ....................................................................................................................96
8.3.15 DMA Transfers .....................................................................................................................97
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