W83977ATG 查看數據表（PDF） - Winbond
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W83977ATG Datasheet PDF : 198 Pages
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W83977ATF/W83977ATG
16.1 FDC ................................................................................................................................... 173
16.2 UART/Parallel.................................................................................................................... 174
16.2.1 Modem Control Timing .......................................................................................................175
16.3 Parallel Port ....................................................................................................................... 176
16.3.1 Parallel Port Timing ............................................................................................................176
16.3.2 EPP Data or Address Read Cycle (EPP Version 1.9) ........................................................177
16.3.3 EPP Data or Address Write Cycle (EPP Version 1.9).........................................................178
16.3.4 EPP Data or Address Read Cycle (EPP Version 1.7) ........................................................179
16.3.5 EPP Data or Address Write Cycle (EPP Version 1.7).........................................................180
16.3.6 Parallel Port FIFO Timing ...................................................................................................180
16.3.7 ECP Parallel Port Forward Timing......................................................................................181
16.3.8 ECP Parallel Port Reverse Timing......................................................................................181
16.4 KBC ................................................................................................................................... 182
16.4.1 Write Cycle Timing .............................................................................................................182
16.4.2 Read Cycle Timing .............................................................................................................182
16.4.3 Send Data to K/B................................................................................................................182
16.4.4 Receive Data from K/B .......................................................................................................183
16.4.5 Input Clock .........................................................................................................................183
16.4.6 Send Data to Mouse...........................................................................................................183
16.4.7 Receive Data from Mouse ..................................................................................................183
16.5 GPIO Write Timing Diagram.............................................................................................. 184
16.6 Master Reset (MR) Timing ................................................................................................ 184
17. APPLICATION CIRCUITS ........................................................................................................... 185
17.1 Parallel Port Extension FDD.............................................................................................. 185
17.2 Parallel Port Extension 2FDD............................................................................................ 186
17.3 Four FDD Mode................................................................................................................. 186
18. ORDERING INFORMATION ....................................................................................................... 187
19. HOW TO READ THE TOP MARKING ........................................................................................ 188
20. PACKAGE DIMENSIONS............................................................................................................ 189
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Publication Release Date: May 2006
Revision 0.6
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