LC72711W 查看數據表（PDF） - SANYO -> Panasonic
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LC72711W Datasheet PDF : 26 Pages
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LC72711W, 72711LW
Specifications
Absolute Maximum Ratings at Ta=25°C, VSS=0V. Items in parentheses refer to the LC72711LW.
Parameter
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable output current (total)
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD
VIN1
VIN2
VOUT1
VOUT2
IOUT1
IOUT2
ITTL
Pd max
Topr
Tstg
Conditions
A0/CL, A1/CE, A2/DI, RST, STNBY
Pins other than VIN1
DO
Pins other than VOUT1
INT, RDY, DREQ, and D0 to D15
Pins other than IOUT1
Total for all the output pins
Ta ≤ 85°C
Ratings
Unit
(-0.3 to +5.5) -0.3 to +7.0
V
-0.3 to +7.0
V
-0.3 to VDD +0.3
V
-0.3 to +7.0
V
-0.3 to VDD +0.3
V
0 to 4.0 mA
0 to 2.0 mA
20 mA
200 mW
--40 to +85
°C
--55 to +125
°C
[LC72711W]
Allowable Operating Ranges at Ta=-40 to +85°C, VSS=0V
Parameter
Supply voltage
High-level input voltage
Low-level input voltage
Oscillator frequency
XIN input sensitivity
Input amplitude
[Serial I/O]
Clock low-level period
Clock high-level period
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
Data latch change time
Data output time
CRC4 change time
Symbol
VDD
VIH1
VIH2
VIL1
VIL2
FOSC
VXI
VMPX
tCL
tCH
tSU
tHD
tEL
tES
tEH
tLC
tDDO
tCRC
Conditions
A0/CL, A1/CE, A2/DI, RST, STNBY
DACK, WR, RD, CS, SP, BUSWD, A3, IOCNT1, IOCNT2
Pins for which VIH1 applies
Pins for which VIH2 applies
This IC operates with a frequency precision of ±250 ppm
With a sine wave input to XIN, capacitor coupling,
VDD=+4.5 to +5.5V
With a 100% modulated composite signal input to
MPXIN, VDD=+4.5 to +5.5V
min
4.5
0.7VDD
0.7VDD
VSS
VSS
400
150
Ratings
typ
7.2
max
5.5
5.5
VDD
0.3VDD
0.3VDD
Unit
V
V
V
V
V
MHz
1500 mVrms
400 mVrms
A0/CL
A0/CL
A0/CL, A2/DI
A0/CL, A2/DI
A0/CL, A1/CE
A0/CL, A1/CE
A0/CL, A1/CE
A1/CE
DO, A0/CL
CRC4, A0/CL
0.7
µS
0.7
µS
0.7
µS
0.7
µS
0.7
µS
0.7
µS
0.7
µS
0.7 µS
277
555 nS
0.7 µS
[LC72711W]
Allowable Operating Ranges: Parallel Interface at Ta=-40 to +85°C, VSS=0V
Parameter
[Parallel I/O]
Address to RD setup
RD to address hold
RD low-level width
RD low-level width (when RDY is used)
RD cycle wait
RDY width (Register read)
RD data hold
Address to WR setup
WR to address hold
WR cycle wait
WR low-level width
WR data hold
RDY output delay
Corrected output RD width
Corrected output RD width
(when RDY is used)
Symbol
Conditions
Ratings
Unit
min
typ
max
tSARD
A0/CL, A1/CE, A2/DI, A3, RD
20
tHARD
A0/CL, A1/CE, A2/DI, A3, RD, tWRDL=>250ns
-20
tWRDL1 RD
250
tWRDL2 RD
100
tCYRD
A0/CL, A1/CE, A2/DI, A3, RD
150
tWRDY RDY
60
tRDH
RD, DATn
0
tSAWR A0/CL, A1/CE, A2/DI, A3, WR
20
tHAWR A0/CL, A1/CE, A2/DI, A3, WR
20
tCYWR A0/CL, A1/CE, A2/DI, A3, WR
150
tWWRL WR
200
tWDH
WR, DATn
0
tDRDY
RD, RDY
0
RD (BUSWD=L 8bits)
300
tWDRD1 RD (BUSWD=H 16bits)
540
RD (BUSWD=L 8bits)
100
tWDRD2 RD (BUSWD=H 16bits)
300
nS
nS
nS
nS
nS
210 nS
nS
nS
nS
nS
nS
nS
30 nS
nS
nS
nS
nS
Continued on next page.
No.6167-2/26
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