SDRAM (Rev.1.31)
Single Data Rate
Apr. '02
MITSUBISHI LSIs
M2V56S20/ 30/ 40 ATP
M2V56S20/ 30/ 40 AKT
256M Synchronous DRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and
ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh,
supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After
tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be
issued, but DESEL or NOP commands must be asserted till then.
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-12
BA0-1
Self Refresh Entry
Self-Refresh
Stable CLK
NOP
new command
X
00
Self Refresh Exit minimum tRFC
for recovery
MITSUBISHI ELECTRIC
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