CXD3526GG 查看數據表（PDF） - Sony Semiconductor

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CXD3526GG

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD3526GG

3. Serial Bus

The serial bus of this IC consists of a host I/F, external ROM I/F and register I/F.

3-1. Host I/F

With this IC, each register setting and data set to built-in RAM are performed over a serial bus. Bus protocol

conforms to I2C bus specifications. Note that this IC does not support multi-slave functions, and that the bus

should be independent from ICs having the other I2C bus specification. Also, when accessing gamma RAM,

always access memory address from odd addresses in 2-byte units. The following restrictions are placed on

the host I/F of this IC.

• Only I2C bus slave operations are performed.

• Standard mode and fast mode are supported. Hs mode is not supported.

• Multi-slave functions are not supported.

• The general call address and start byte of the slave address are not acknowledged.

• C bus compatibility is not supported.

• Acknowledgment is not performed for 10-bit slave addresses.

• Low is not asserted for HSCL. (Wait control is not performed.)

(1) "Start" conditions

Read and write operations enter "Start" status by switching HSDA input from high to low level while HSCL input

is high.

(2) "Stop" conditions

"Stop" results by switching HSDA input from low to high while HSCL input is high. Setting "Stop" status causes

read processing to terminate during read operations, and causes the input of write data to terminate during

write operations.

HSDA

HSCL

"Start"

"Stop"

"Start" Conditions and "Stop" Conditions

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