CXD3526GG 查看數據表（PDF） - Sony Semiconductor

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CXD3526GG

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD3526GG

3-3. External ROM I/F

When operating the external ROM I/F, operations start by setting the serial bus register from the host I/F. The

serial bus on the ROM side is used to access the external EEPROM. Bus protocol conforms to I2C bus

specifications. Also, the following restrictions are placed on the external ROM I/F of this IC.

• Only master operations are performed.

• Standard mode and fast mode are supported. Hs mode is not supported.

• Multi-master functions are not supported.

• The general call address and start byte of the slave address are not generated.

• C bus compatibility is not supported.

• A memory address space of up to 512K bytes is supported.

• Wait control by RSCL is not supported.

• 10-bit slave addresses are not supported.

(1) External ROM I/F clock settings

The frequency of the clock signal supplied to the external EEPROM by the RSCL pin is set using RSCL_SEL

of the serial bus control registers. Set this value based on the operating frequency of the IC as given in the

table below so that the frequency output by the RSCL pin is appropriate for the specifications of the external

EEPROM.

RSCL_SEL

00

01

10

Operating frequency

35MHz or less

70MHz or less

94.5MHz or less

11

100MHz or less

(2) External EEPROM memory capacity setting

With this IC, slave addresses and memory addresses are generated in accordance with the memory capacity

set for the external EEPROM. The memory capacity of the external EEPROM is set using ROM_MAP of the

serial bus control registers.

ROM_MAP

00

01

10

11

Usable memory size

512K-bit (65,536 × 8-bit)

256K-bit (32,768 × 8-bit)

128K-bit (16,384 × 8-bit)

64K-bit (8,192 × 8-bit)

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