CXD3526GG 查看數據表（PDF） - Sony Semiconductor

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CXD3526GG

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD3526GG

(5) Refresh and write-back operations

This IC includes a function that allows an external EEPROM to automatically refresh the internal RAM. This

function has the four modes described below.

• Self-refresh mode

• Forced refresh mode

• Write-back mode

• Refresh stop mode

Each mode is started by writing the specified mode into REF_MODE of the refresh register.

In self-refresh mode, the IC detects that the vertical blanking period has been entered and, using the value

specified in the external EEPROM transfer count register, uses the continuous read operation to transfer data

of the size "transfer count plus 1" to the external ROM I/F. The data read using the continuous read transfer is

written into the internal RAM.

When the transfer of the all data for the data size is completed, the access area for the internal RAM is

changed, continuous read transfer is executed indefinitely until self-refresh mode is exited, and refresh

operations are automatically carried out on the internal RAM.

In forced refresh mode, continuous read transfer from the external EEPROM is performed for the RAM area

specified by REF_RSEL of the refresh RAM select register, and the read data is written to the internal RAM.

When the transfer of all data for the specified RAM area is completed, REF_END of the refresh status register

set to a flag indicating the operation has ended, and operations stop.

If forced refresh operations are to be performed for the entire internal RAM, first set the refresh RAM select

register to gamma RAM (R) and perform the forced refresh operation. Since the refresh RAM select register is

automatically set to the next RAM area after all data is transferred, refresh for the entire RAM can be

completed by repeating the forced refresh operation five times.

In write-back mode, continuous write transfer is performed from the RAM area specified by REF_RSEL of the

refresh RAM select register to the external EEPROM. When the transfer of all data for the specified RAM area

is completed, REF_END of the refresh status register set to a flag indicating the operation has ended, and

operations stop.

If write-back operations are to be performed for the entire internal RAM, first set the refresh RAM select

register to gamma RAM (R) just as for forced refresh operation, and then perform the write-back operation.

Since the refresh RAM select register is automatically set to the next RAM area after all data is transferred,

write-back for the entire RAM can be completed by repeating the write-back operation five times.

In refresh stop mode, the external ROM I/F does not operate and nothing is output on the serial bus.

(6) Forced reset of the external ROM I/F control circuit

With this IC, forced reset is possible in case a problem occurs with the external ROM I/F and the internal

circuit becomes locked. Forced reset initializes only the external ROM I/F control circuit by writing "1" to

ROM_RST of the refresh register. Normal operations are allowed after initialization is complete.

3-4. Register I/F Control Circuit

The register I/F control circuit transfers data between the host I/F and the external ROM I/F. Register data

other than RAM data is stored here. Since registers have a double buffer configuration, data in the first buffer is

synchronized with the internal VD and reflected in the second buffer, while data in the second buffer is input to

each block. Note, however, that data in the serial bus control register has a single buffer configuration.

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