CXD1961AQ 查看數據表（PDF） - Sony Semiconductor

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CXD1961AQ

DVB-S Frontend IC (QPSK demodulation + FEC)

Sony Semiconductor 

CXD1961AQ

Sub address 10 (hex)

Write

AGC/RST AGC and Reset

MAGC

AGC mode 0: normal mode 1: bus control mode

In normal mode, PWM output is controlled so that I2 + Q2 (register 00hex) should

become approximately equal to the reference level set in register 21 (hex). In bus

control mode, data of the register 21 (hex) is directly converted to PWM output.

PAGC

MVSYNC

AGC polarity 0: For tuner whose gain increases by higher AGC control voltage

1: For tuner whose gain increases by lower AGC control voltage

Select mode according to tuner AGC type.

Input 0

CKVSEL

QPRST

VTRST

RSRST

CKV (Pin 69) output mode

0: symbol clock output

1: sampling clock output

1: QPSK block reset (set 0 for normal operation)

To reset QPSK block, set this bit to 1 and then set this bit to 0 again.

1: Viterbi block reset (set 0 for normal operation)

Reset operation is same as QPRST.

1: Deinterleaver and Reed-solomon block reset (set 0 for normal operation)

Reset operation is same as QPRST.

VCORST

1: NCO block reset (set 0 for normal operation)

Reset operation is same as QPRST.

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