FZL4146 查看數據表（PDF） - Infineon Technologies
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FZL4146 Datasheet PDF : 14 Pages
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FZL 4146
Operating Range
Parameter
Supply voltage11)
Supply voltage12)
Supply voltage13)
Supply voltage rise
Junction temperature
Time-determining capacitor of
the clock generator
Input voltage
Current at output SQ
Symbol
VS
VS
VS
dVS/dt
Tj
Ce
VDI, ENA, TS
ISQ
Limit Values
min. max.
4.5
40
VTS + 3 40
10
40
–1
1
– 25 150
1
100
–2
40
–1
6
Unit
V
V
V
V/µs
°C
nF
V
mA
Remarks
VTS = 0 … 1.5 V
VTS = 1.5 … 7 V
VTS = VS
20)
10)
14) 15) 16) 17) 19)
Notes: 9) W pins that remain open, must be connected to VS.
10) The Ce value depends on the desired pulse width tp during short circuit.
It applies: Ce = 0.25 mS x tp.
11) At an input threshold = 1.5 V
12) At an input threshold = 1.5 V to 7 V
13) At an input threshold = 7 V
14) This function is also ensured for 40 V ≤ VS ≤ 45 V and – 40 °C ≤ Tj ≤ – 25 °C as long as
0 V ≤ VDI, ENA, TS ≤ 40 V.
15) The outputs Q are disabled even if – 3 V ≤ VDI, ENA ≤ – 2 V or – 1 mA ≤ IDI, ENA ≤ 50 µA and
VS – 5 V ≤ VW ≤ VS + 5 V, max. 45 V.
16) The outputs Q are enabled even if 40 V ≤ VDI, ENA ≤ 45 V and VS – 0.2 V ≤ VW ≤ VS + 5 V,
max. 45 V.
17) Current limiting and disabling of outputs Q are ensured even if 40 V ≤ VDI, ENA ≤ 45 V and
VS – 5 V ≤ VW ≤ VS – 0.4 V.
18) Dynamic charge reversal of a 2-nF capacitor as in figure 1 is permissible (corresponds
to short circuit to conducting output in P-channel MOSFET)
19) Proper working of the IC is also ensured if, before VS is turned-On, an input voltage
VDI, ENA is present in the permissible range (footnote 15).
20) At 10 V/µs short-term malfunction is possible, but never a latch-up.
Semiconductor Group
8
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