Q67100-Q727 查看數據表（PDF） - Siemens AG

零件编号

产品描述 (功能)

生产厂家

Q67100-Q727

256k × 16-Bit Dynamic RAM

Siemens AG 

HYB 514171BJ-50/-60

256k × 16 DRAM

WE

UCAS

LCAS

&

No.2 Clock

Generator

9

Column

Address

Buffers (9)

A0

A1

Refresh

A2

Controller

A3

A4

A5

Refresh

A6

Counter (9)

A7

9

A8

9

Row

Address

Buffers (9)

RAS

No.1 Clock

Generator

Block Diagram

Semiconductor Group

I/O1 I/O2 . . . I/O16

. . ..

Data In

Buffer

16

Data Out

Buffer

OE

16

9

Column

Decoder

Sense Amplifier

16

I/O Gating

512

x 16

9

...

Row

Decoder

512

...

Memory Array

512 x 512 x 16

Substrate Bias

Generator

V CC

V SS

SPB02827

4

1998-10-01

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