MAX4612EPD 查看數據表（PDF） - Maxim Integrated

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MAX4612EPD

Low-Voltage, Quad, SPST CMOS Analog Switches

Maxim Integrated 

Low-Voltage, Quad, SPST

CMOS Analog Switches

MAX4610

TSSOP/SO/ DIP QFN

1, 3, 8, 11

1, 3,

8, 11

—

—

PIN

MAX4611

TSSOP/SO/DIP QFN

—

—

1, 3, 8, 11

1, 3,

8, 11

—

—

—

—

—

2, 4, 9, 10

13, 5, 6, 12

7

—

2, 4,

9, 10

14, 5,

6, 13

7

—

2, 4, 9, 10

13, 5, 6, 12

7

—

2, 4,

9, 10

14, 5,

6, 13

7

—

12, 15

—

12, 15

14

16

14

16

—

—

—

—

Pin Description

MAX4612

TSSOP/SO/DIP QFN

—

—

—

—

1, 8

1, 8

3, 11

2, 4, 9, 10

13, 5, 6, 12

7

3, 11

2, 4,

9, 10

14, 5,

6, 13

7

—

12, 15

14

16

—

—

NAME

FUNCTION

NO1–NO4

Analog Switch Normally Open

Terminals

NC1–NC4

Analog Switch Normally Closed

Terminals

NO1, NO3

Analog Switch Normally Open

Terminals

NC2, NC4

Analog Switch Normally Closed

Terminals

COM1–COM4

Analog Switch Common

Terminals

IN1–IN4 Logic-Control Digital Input

GND

N.C.

V+

EP

Ground. Connect to digital

ground.

No Connection. Not internally

connected.

Positive Analog and Digital-

Supply Voltage Input. Internally

connected to substrate.

Exposed Pad (QFN only).

Connect to V+.

Applications Information

Power-Supply Sequencing

and Overvoltage Protection

Do not exceed the absolute maximum ratings, because

stresses beyond the listed ratings may cause permanent

damage to the devices.

Proper power-supply sequencing is recommended for all

CMOS devices. Always apply V+ before applying analog

signals or logic inputs, especially if the analog or logic

signals are not current limited. If this sequencing is not

possible, and if the analog or logic inputs are not current

limited to 20mA, add a small-signal diode (D1) as shown

in Figure 1. If the analog signal can dip below GND, add

D2. Adding protection diodes reduces the analog signal

range to a diode drop (about 0.7V) below V+ (for D1),

and to a diode drop above ground (for D2). Leakage is

unaffected by adding the diodes. On-resistance increas-

es by a small amount at low supply voltages. Maximum

supply voltage (V+) must not exceed 13V.

Adding protection diodes causes the logic thresholds to

be shifted relative to the power-supply rails. This can be

POSITIVE SUPPLY

V+

MAX4610

MAX4611

MAX4612

NO_

COM_

Vg

Figure 1. Overvoltage Protection Using Two External Blocking

Diodes

significant when low supply voltages (+5V or less) are

used. With a +5V supply, TTL compatibility is not guar-

anteed when protection diodes are added. Driving IN1

and IN2 all the way to the supply rails (i.e., to a diode

drop higher than the V+ pin, or to a diode drop lower

than the GND pin) is always acceptable.

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