SK70708 查看數據表（PDF） - Intel

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SK70708

1168 Kbps HSDL Data Pump Chip Set

Intel 

SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set

Table 1. SK70704 ACC Pin Assignments/Signal Descriptions (Continued)

Group

Power

Clock and

Control

Pin #

10

12

23

24

6

15

20

3

4

5

27

28

1

Data Input

and

2

Output

25

26

Analog

Input

11

Symbol

PGND

RVCC

TVCC

DVCC

DGND

RGND

TGND

FS

DTR

CK37M

TCK4M

AGCKIK

AD1

AD0

TSGN

TMAG

IBIAS

I/O

Description

I PLL Ground. 0 V.

I Power supply. + 5 V (± 5%).

I Power supply. + 5V (± 5%).

I Digital Power Supply. +5 V (± 5%).

I DVCC Ground. 0V.

I RVCC Ground. 0V.

I TVCC Ground. 0V.

I 584 kHz clock. Input from HDX FS.

I Serial control data. Input from the HDX at 18.688 Mbps.

O

37.376 MHz HDSL Reference Clock. Used as the receive timing reference for the

HDX. Tie to HDX CK37M.

I 4.672 MHz Clock. Input from HDX TCK4M.

O AGC adjust signal. Output to HDX AGCKIK.

O A-to-D converter data line 1. Connect to HDX AD1.

O A-to-D converter data line 0. Connect to HDX AD0.

I Transmit quat sign. Input from HDX.

I Transmit quat magnitude. Input from HDX.

I Input BIAS. Provides input bias current.

10

Datasheet

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