SK70708 查看數據表（PDF） - Intel
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SK70708 Datasheet PDF : 54 Pages
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SK70704/SK70707 or SK70708 — 1168 Kbps HSDL Data Pump Chip Set
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SK70704/SK70707 or SK70708 Block Diagram ................................................... 7
Package Markings................................................................................................. 7
SK70704 ACC Pin Locations ................................................................................ 8
SK70707/SK70708 HDX Pin Assignments ........................................................... 9
HDX/ACC Interface – Relative Timing ................................................................ 18
HDX/ACC Framer Interface – Relative Timing.................................................... 20
Model for HDSL Data Pump and HDSL Framer Applications ............................. 21
LTU Data Pump Activation State Machine.......................................................... 32
LTU HDSL Framer Activation State Machine...................................................... 32
NTU Data Pump Activation State Machine ......................................................... 34
NTU HDSL Framer Activation State Machine ..................................................... 35
HDSL Synchronization State Machine ................................................................ 36
PCB Layout Guidelines ....................................................................................... 39
Typical Support Circuitry for LTU Applications.................................................... 40
Typical Support Circuitry for NTU Applications ................................................... 42
SK70707/SK70708 HDX Control and Status Signals (Hardware Mode) ............ 43
ACC Normalized Pulse Amplitude Transmit Template ....................................... 45
ACC Transmitter Timing...................................................................................... 46
Upper Bound of Transmit Power Spectral Density.............................................. 46
ACC Receiver Syntax and Timing....................................................................... 47
HDX/HDSL Data Interface Timing....................................................................... 49
Reset and Interrupt Timing (mP Control Mode) ................................................. 51
Parallel Data Channel Timing ............................................................................ 52
ACC Plastic Leaded Chip Carrier Package Specifications ................................ 53
HDX Plastic Leaded Chip Carrier Package Specifications ................................. 54
Tables
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SK70704 ACC Pin Assignments/Signal Descriptions ........................................... 9
SK70707/SK70708 HDX Pin Assignments/Signal Descriptions ......................... 11
ACC Transmit Control ......................................................................................... 17
HDX/ACC Serial Port Word Bit Definitions ( Figure 5) ........................................ 18
HDSL Framer TDATA Requirements .................................................................. 19
Register Summary .............................................................................................. 23
Main Control Register WR0 ................................................................................ 23
Interrupt Mask Register WR2.............................................................................. 24
Read Coefficient Select Register WR3 ............................................................... 25
Main Status Register RD0................................................................................... 25
Receiver Gain Word Register ............................................................................. 26
Noise Margin Register RD2
Noise Margin Coding126
Coefficient Read Register ................................................................................... 28
Activation Status Register RD5........................................................................... 28
Receiver AGC and FFE Step Gain Register RD6............................................... 29
Data Pump/Framer Activation State Machine Correspondences........................ 30
Activation – Synchronization ............................................................................... 33
Components for Suggested Circuitry (Figure 14 and Figure 15) ........................ 40
Transformer Specifications
(Figure 14 and Figure 15, Reference T1)41
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Datasheet
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