SC28C198A1A 查看數據表（PDF） - Philips Electronics

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SC28C198A1A

Octal UART for 3.3V and 5V supply voltage

Philips Electronics 

Philips Semiconductors

Octal UART for 3.3V and 5V supply voltage

Product specification

SC28L198

If ’with parity’ or ’force parity’ is selected, a parity bit is added to the

transmitted character and the receiver performs a parity check on

incoming data. MR1[4:3] = 11 selects the channel to operate in the

special wake up mode.

MR1[2]: Parity Type Select

This bit sets the parity type (odd or even) if the ’with parity’ mode is

programmed by MR1[4:3], and the polarity of the forced parity bit if

the ’force parity’ mode is programmed. It has no effect if the ’no

parity’ mode is programmed. In the special ’wake up’ mode, it

selects the polarity of the A/D bit. The parity bit is used to an

address or data byte in the ’wake up’ mode.

MR1[1:0]: Bits per Character Select

This field selects the number of data bits per character to be

transmitted and received. This number does not include the start,

parity, or stop bits.

Table 5. MR2 – Mode Register 2

The MR2 register provides basic channel setup control that may need more frequent updating.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bits 7:6

Bit 5

Bit 4

Bit 3:2

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Channel Mode

TxRTS Control

CTSN Enable Tx

RxINT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 00 = normal

01 = Auto echo

0 = No

1 = Yes

0 = No

1 = Yes

00 = RRDY

01 = Half Full

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 10 = Local loop

10 = 3/4 Full

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 11 = Remote loop

11 = Full

Bit 1:0

Stop Length

00 = 1.0

01 = 1.5

10 = 2.0

11 = 9/16

MR2[7:6] – Mode Select

The Octal UART can operate in one of four modes: MR2[7:6] = b’00

is the normal mode, with the transmitter and receiver operating

independently.

MR2[7:6] = b’01 places the channel in the automatic echo mode,

which automatically re transmits the received data. The following

conditions are true while in automatic echo mode:

The received parity is not checked and is not regenerated for

transmission, i.e., the transmitted parity bit is as received.

The receiver must be enabled, but the transmitter need not be

enabled.

Character framing is not checked, and the stop bits are

re-transmitted as received.

A received break is echoed as received until the next valid start

bit is detected.

Received data is re–clocked and re–transmitted on the TxD

output.

The receive clock is used for the transmitter.

The receiver must be enabled, but the transmitter need not be

enabled.

The TxRDY and TxEMT status bits are inactive.

The received parity is checked, but is not regenerated for

transmission,

i.e., transmitted parity bit is as received.

MR2[5] – Transmitter Request to Send Control

This bit controls the deactivation of the RTSN output (I/O2) by the

transmitter. This output is manually asserted and negated by

appropriate commands issued via the command register. MR2[5] =

1 causes RTSN to be reset automatically one bit time after the

characters in the transmit shift register and in the TxFIFO (if any)

are completely transmitted (includes the programmed number of

stop bits if the transmitter is not enabled). This feature can be used

to automatically terminate the transmission of a message as follows:

Character framing is checked, but the stop bits are re-transmitted

as received.

A received break is echoed as received until the next valid start

bit is detected

Program auto reset mode: MR2[5]= 1.

Enable transmitter.

Assert RTSN via command.

Send message.

. CPU to receiver communication continues normally, but the CPU

to transmitter link is disabled.

Two diagnostic modes can also be selected.

MR2[7:6] = b’10 selects local loop back mode. In this mode:

The transmitter output is internally connected to the receiver

input.

The transmit clock is used for the receiver.

The TxD output is held high.

The RxD input is ignored.

The transmitter must be enabled, but the receiver need not be

enabled.

CPU to transmitter and receiver communications continue

normally.

The second diagnostic mode is the remote loop back mode,

selected by MR2[7:6] = b’11. In this mode:

After the last character of the message is loaded to the TxFIFO,

disable the transmitter. Before disabling the transmitter be sure

the Status Register TxEMT bit is NOT set (i.e., the transmitter is

not underrun). The underrun condition is indicated by the

TxEMT bit in the SR being set. The condition occurs

immediately upon enabling the transmitter and persists until a

character is loaded to the TxFIFO. The Underrun condition will

not be a problem as long as the controlling processor keeps up

with the transmitter data flow. The proper operation of this

feature assumes that the transmitter is busy (not underrun) when

the disable is issued.

The last character will be transmitted and RTSN will be reset one

bit time after the last stop bit.

NOTE: When the transmitter controls the RTSN pin, the meaning of

the pin is COMPLETELY changed. It has nothing to do with the

normal RTSN/CTSN “handshaking”. It is usually used to mean “end

of message” and to “turn the line around” in simplex

communications.

Received data is re–clocked and re–transmitted on the TxD

output.

The receive clock is used for the transmitter.

Received data is not sent to the local CPU, and the error status

conditions are inactive.

MR2[4] – Clear to Send Control

The state of this bit determines if the CTSN input (I/O0) controls the

operation of the transmitter. If this bit is 0, CTSN has no effect on

the transmitter. If this bit is a 1, the transmitter checks the state of

CTSN each time it is ready to begin sending a character. If it is

1999 Jan 14

20

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