WM8199 查看數據表（PDF） - Cirrus Logic

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WM8199

20MSPS 16-bit CCD Digitiser

Cirrus Logic 

WM8199

Production Data

POWER MANAGEMENT

Power management for the device is performed via the Control Interface. The device can be powered

on or off completely by setting the EN bit and SELPD bit low. Alternatively, when control bit SELPD is

high, only blocks selected by further control bits (SELDIS[3:0]) are powered down. This allows the

user to optimise power dissipation in certain modes, or to define an intermediate standby mode to

allow a quicker recovery into a fully active state. In Line-by-line operation, the green and blue channel

PGAs are automatically powered down.

All the internal registers maintain their previously programmed value in power down modes and the

Control Interface inputs remain active. Table 3 summarises the power down control bit functions.

EN

SELDPD

0

0

Device completely powers down.

1

0

Device completely powers up.

X

1

Blocks with respective SELDIS[3:0] bit high are disabled.

Table 3 Power Down Control

LINE-BY-LINE OPERATION

Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a

full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to

accommodate this type of signal the WM8199 can be set into Monochrome mode, with the input

channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8199

can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is

set the green and blue processing channels are powered down and the device is forced internally to

only operate in MONO mode (because only one colour is sampled at a time) through the red channel.

Figure 22 shows the signal path when operating in colour line-by-line mode.

VRLC/VBIAS

VSMP MCLK

RINP

GINP

BINP

CL

RS VS TIMING CONTROL

RLC

RLC

INPUT

MUX

CDS

R

OFFSET

G MUX

B

8 OFFSET

DAC

+ PGA

16- DATA

+

BIT

I/O

R

PGA

G MUX

B

8

I/P SIGNAL

POLARITY

ADJUST

ADC PORT

RLC

RLC 4

DAC

CONFIGURABLE

SERIAL/

PARALLEL

CONTROL

INTERFACE

OP[7:0]

SEN/STB

SCK/RNW

SDI/DNA

RLC/ACYC

NRESET

Figure 22 Signal Path When in Line-by-Line Mode

In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto-

cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit.

See figure 4 for detailed timing. The multiplexers change on the first MCLK rising edge after

RLC/ACYC is taken high. A write to the auto-cycle reset register causes these multiplexers to be

reset; selecting the RINP pin and the RED offset/gain registers. Alternatively, all three multiplexers

can be controlled via the serial interface by writing to register bits INTM[1:0] to select the desired

colour. It is also possible for the input multiplexer to be controlled separately from the PGA and

Offset multiplexers. Table 4 describes all the multiplexer selection modes that are possible.

FME ACYCNRLC

NAME

DESCRIPTION

0

0

Internal,

Input mux, offset and gain registers determined by

no force mux internal register bits INTM1, INTM0.

0

1

Auto-cycling, Input mux, offset and gain registers auto-cycled, RINP

no force mux → GINP → BINP → RINP… on RLC/ACYC pulse.

1

0

Internal,

Input mux selected from internal register bits FM1, FM0;

force mux

Offset and gain registers selected from internal register

bits INTM1, INTM0.

1

1

Auto-cycling, Input mux selected from internal register bits FM1, FM0;

force mux

Offset and gain registers auto-cycled, RED → GREEN

→ BLUE → RED… on RLC/ACYC pulse.

Table 4 Colour Selection Description in Line-by-Line Mode

w

PD, Rev 4.4, July 2008

21

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