W77E516 查看數據表（PDF） - Nuvoton Technology
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W77E516 Datasheet PDF : 92 Pages
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W77E516A
ENP: In System Programming Mode Enable. Set this be to launch the ISP mode. Device will
operate ISP procedures, such as Erase, Program and Read operations, according to
correlative SFRs settings. During ISP mode, device achieves ISP operations by the way of
IDLE state. In the other words, device is not indeed in IDLE mode is set bit PCON.1 while ISP
is enabled. Clear this bit to disable ISP mode, device get back to normal operation including
IDLE state.
Port 2
Bit:
7
6
5
4
3
2
1
0
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
Mnemonic: P2
Address: A0h
P2.7 − 0: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper
address bits for accesses to external memory.
Port 4 Chip-Select Polarity
Bit:
7
6
5
4
3
2
1
0
P43INV P42INV P42INV P40INV -
-
-
P0UP
Mnemonic: P4CSIN
Address: A2h
P4xINV: The active polarity of P4.x when set it as chip-select signal. High = Active High. Low =
Active Low.
P0UP: Enable Port 0 weak pull up.
Port 4
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
P4.3 P4.2 P4.1 P4.0
Mnemonic: P4
Address: A5h
P4.3 – 0: Port 4 is a bi-directional I/O port with internal pull-ups. Port 4 can not use bit-addressable
instruction (SETB or CLR).
Interrupt Enable
Bit:
7
6
5
4
3
2
1
0
EA
ES1 ET2
ES
ET1 EX1 ET0 EX0
Mnemonic: IE
EA: Global enable. Enable/disable all interrupts except for PFI.
ES1: Enable Serial Port 1 interrupt.
ET2: Enable Timer 2 interrupt.
ES: Enable Serial Port 0 interrupt.
ET1: Enable Timer 1 interrupt
Address: A8h
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