APA3160A 查看數據表（PDF） - Anpec Electronics
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APA3160A Datasheet PDF : 38 Pages
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APA3160A
Function Description (Cont.)
I2C Serial Control Interface
The APA3160A DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol. Besides, it
provides both 100kHz and 400kHz data transfer rates to single and multiple bytes write and read operations.
This is a slave only device, and it doesn’t support a multi-master bus environment or wait state insertion. The function
of the control interface is to read device status and to program the registers of the device.
The DAP supports the standard-mode I2C bus operation (100kHz maximum) and the fast I2C bus operation (400kHz
maximum). Without I2C wait cycles, the DAP performs I2C operations.
General I2C Operation
The I2C bus uses SDA (data) and SCL (clock) to communicate between integrated circuits in a system. Data is
transferred on the bus serially one bit at a time. With the most significant bit (MSB) transferred first, the address and
data can be transferred in byte (8bit) format. In addition, each byte transferred on the bus is acknowledged by the
receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start
condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the SDA when the clock is high to indicate start and stop conditions. A high-to-low
transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data bit transitions must
occur within the low time of the clock. These conditions are shown in Figure 10. The master generates the 7bit slave
address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge
condition. The APA3160A holds SDA low during the acknowledge clock to indicate an acknowledgment. When this
occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA
and SCL signals to set the high level for the bus.
SDA
7-Bit Slave Address
R/ A 8-Bit Register Address (N) A
W
8-Bit Register Data for
Address (N)
A
8-Bit Register Data for
Address (N)
A
76543210 76543210 76543210 76543210
SCL
Start
Stop
Figure 10. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word
transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in
Figure 10.
The 7bit address for APA3160A is 0011 010 (0x34). APA3160A address can be changed from 0x34 to 0x38 by writing
0x38 to device address register 0xF9.
Copyright © ANPEC Electronics Corp.
15
Rev. A.6 - Jan., 2013
www.anpec.com.tw
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