Nexperia
74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
12. Abbreviations
Table 10. Abbreviations
Acronym
CDM
CMOS
ESD
HBM
LSTTL
MM
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
Low-power Schottky Transistor-Transistor Logic
Machine Model
13. Revision history
Table 11. Revision history
Document ID
74AHC_AHCT74 v.8
Modifications:
74AHC_AHCT74 v.7
Modifications:
74AHC_AHCT74 v.6
Modifications:
74AHC_AHCT74 v.5
Modifications:
74AHC_AHCT74 v.4
74AHC_AHCT74 v.3
74AHC_AHCT74 v.2
74AHC_AHCT74 v.1
Release date Data sheet status
20200422
Product data sheet
Change notice Supersedes
-
74AHC_AHCT74 v.7
• The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Section 5.1: Corrected pin configuration drawings (errata).
• Table 4: Derating values for Ptot total power dissipation updated.
• Fig. 12: Package outline drawing SOT762-1 (DHVQFN14) updated.
20150421
Product data sheet
-
74AHC_AHCT74 v.6
• Table 7: minimum fmax values at 3.0 V to 3.6 V for 74AHC74 corrected (errata).
20141020
Product data sheet
-
74AHC_AHCT74 v.5
• Table 3 corrected (errata).
20080609
Product data sheet
-
74AHC_AHCT74 v.4
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 6: the conditions for input leakage current have been changed.
20050207
Product data sheet
-
74AHC_AHCT74 v.3
20040429
Product specification -
74AHC_AHCT74 v.2
19990923
Product specification -
74AHC_AHCT74 v.1
19990805
Product specification -
-
74AHC_AHCT74
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 22 April 2020
© Nexperia B.V. 2020. All rights reserved
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