A3977(2013) 查看數據表（PDF） - Allegro MicroSystems

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A3977
(Rev.:2013)

Microstepping DMOS Driver with Translator

Allegro MicroSystems 

A3977

Microstepping DMOS Driver with Translator

Functional Description (cont’d)

Synchronous Rectification. When a PWM off-cycle is

triggered by an internal fixed off-time cycle, load current

will recirculate according to the decay mode selected by

the control logic. The A3977 synchronous rectification fea-

ture will turn on the appropriate MOSFETs during the cur-

rent decay and effectively short out the body diodes with

the low rDS(on) driver. This will reduce power dissipation

significantly and eliminate the need for external Schottky

diodes for most applications.

The synchronous rectification can be set in either ac-

tive mode or disabled mode.

Active Mode. When the SR input is logic low, active

mode is enabled and synchronous rectification will occur.

This mode prevents reversal of the load current by turning

off synchronous rectification when a zero current level is

detected. This prevents the motor winding from conduct-

ing in the reverse direction.

Disabled Mode. When the SR input is logic high, syn-

chronous rectification is disabled. This mode is typically

used when external diodes are required to transfer power

dissipation from the A3977 package to the external diodes.

Timing Requirements

(TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground)

A. Minimum Command Active Time

Before Step Pulse (Data Set-Up Time) ..... 200 ns

B. Minimum Command Active Time

After Step Pulse (Data Hold Time) ........... 200 ns

C. Minimum STEP Pulse Width ...................... 1.0 μs

D. Minimum STEP Low Time ......................... 1.0 μs

E. Maximum Wake-Up Time ......................... 1.0 ms

Allegro MicroSystems, LLC

9

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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