DS17287-5 查看數據表（PDF） - Maxim Integrated

零件编号

产品描述 (功能)

生产厂家

DS17287-5

Real-Time Clocks

Maxim Integrated 

DS17285/DS17287/

DS17485/DS17487/

DS17885/DS17887

Power-Down/Power-Up

Considerations

The RTC function continues to operate, and all the RAM,

time, calendar, and alarm memory locations remain non-

volatile regardless of the level of the VCC input. VBAT or

VBAUX must remain within the minimum and maximum

limits when VCC is not applied. When VCC falls below

VPF, the device inhibits all access, putting the part into

a low-power mode. When VCC is applied and exceeds

VPF (power-fail trip point), the device becomes acces-

sible after tREC, if the oscillator is running and the oscil-

lator countdown chain is not in reset (Register A). This

time period allows the system to stabilize after power

is applied. If the oscillator is not enabled, the oscilla-

tor enable bit is enabled on powerup, and the device

becomes immediately accessible.

Power Control

The power control function is provided by a precise,

temperature-compensated voltage reference and a com-

parator circuit that monitors the VCC level. The device is

fully accessible and data can be written and read when

VCC is greater than VPF. However, when VCC falls below

VPF, the device inhibits read and write access. If VPF is

less than VBAT, the device power is switched from VCC

to the higher of VBAT or VBAUX when VCC drops below

VPF. If VPF is greater than the higher of VBAT or VBAUX,

the device power is switched from VCC to the higher of

VBAT or VBAUX when VCC drops below the higher backup

source. The registers are maintained from the VBAT or

VBAUX source until VCC is returned to nominal levels.

After VCC returns above VPF, read and write access is

allowed after tREC.

Table 2. Power Control

SUPPLY CONDITION

VCC < VPF, VCC <

(VBAT | VBAUX)

VCC < VPF, VCC >

(VBAT | VBAUX)

VCC > VPF, VCC <

(VBAT | VBAUX)

VCC > VPF, VCC >

(VBAT | VBAUX)

READ/WRITE

ACCESS

No

No

Yes

Yes

POWERED BY

VBAT or VBAUX

VCC

VCC

VCC

Real-Time Clocks

Time, Calendar, and Alarm

Locations

The time and calendar information is obtained by read-

ing the appropriate register bytes. The time, calendar,

and alarm are set or initialized by writing the appropriate

register bytes. The contents of the 12 time, calendar, and

alarm bytes can be either binary or binary-coded deci-

mal (BCD) format. Tables 3A and 3B show the BCD and

binary formats of the 12 time, date, and alarm registers,

control registers A to D, plus the two extended registers

that reside in bank 1 only (bank 0 and bank 1 switching is

explained later in this text).

The day-of-week register increments at midnight, incre-

menting from 1 through 7. The day-of-week register is

used by the daylight saving function, and so the value 1

is defined as Sunday. The date at the end of the month

is automatically adjusted for months with fewer than 31

days, including correction for leap years.

Before writing the internal time, calendar, and alarm

registers, the SET bit in Register B should be written to

logic 1 to prevent updates from occurring while access is

being attempted. In addition to writing the 12 time, calen-

dar, and alarm registers in a selected format (binary or

BCD), the data mode bit (DM) of Register B must be set

to the appropriate logic level. All 12 time, calendar, and

alarm bytes must use the same data mode. The set bit in

Register B should be cleared after the data mode bit has

been written to allow the real time clock to update the time

and calendar bytes. Once initialized, the real time clock

makes all updates in the selected mode. The data mode

cannot be changed without reinitializing the 12 data bytes.

Tables 3A and 3B show the BCD and binary formats of the

12 time, calendar, and alarm locations.

The 24-12 bit cannot be changed without reinitializing the

hour locations. When the 12-hour format is selected, the

high order bit of the hours byte represents PM when it is

logic 1. The time, calendar, and alarm bytes are always

accessible because they are double-buffered. Once per

second, the eight bytes are advanced by one second and

checked for an alarm condition.

If a read of the time and calendar data occurs during an

update, a problem exists where seconds, minutes, hours,

etc., may not correlate. The probability of reading incor-

rect time and calendar data is low. Several methods of

avoiding any possible incorrect time and calendar reads

are covered later in this text.

www.maximintegrated.com

Maxim Integrated │  12

Share Link: