DS17885S-5 查看數據表（PDF） - Maxim Integrated
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DS17885S-5 Datasheet PDF : 31 Pages
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DS17285/DS17287/
DS17485/DS17487/
DS17885/DS17887
Real-Time Clocks
Table 3B. Time, Calendar, and Alarm Data Modes—Binary Mode (DM = 1)
ADDRESS BIT 7
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FUNCTION
RANGE
00h
0
0
Seconds
Seconds
00–3B
01h
0
0
Seconds
Seconds Alarm
00–3B
02h
0
0
Minutes
Minutes
00–3B
03h
0
0
Minutes
Minutes Alarm
00–3B
04h
AM/PM
0
0
0
0
Hours
Hours
Hours
1–0C + AM/PM
00–17
05h
AM/PM
0
0
0
0
Hours
Hours
Hours Alarm
1–0C + AM/PM
00–17
06h
0
0
0
0
0
Day
Day
01–07
07h
0
0
0
Date
Date
01–1F
08h
0
0
0
0
Month
Month
01–0C
09h
0
Year
Year
00–63
0Ah
UIP
DV2 DV1 DV0 RS3 RS2 RS1 RS0
Control
—
0Bh
SET
PIE
AIE
UIE SQWE DM 24/12 DSE
Control
—
0Ch
IRQF
PF
AF
UF
0
0
0
0
Control
—
0Dh
VRT
0
0
0
0
0
0
0
Control
—
Bank 1, 48h
10 Century
Century
Century
00–63
Bank 1, 49h
10 Date
Date
Date Alarm
01–1F
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds reg-
ister, 0 bits in the time and date registers can be written to 1, but can be modified when the clock updates. 0 bits should always be
written to 0 except for alarm mask bits.
Control Registers
The four control registers (A, B, C, and D) reside in both
bank 0 and bank 1. These registers are accessible at all
times, even during the update cycle.
Register A (0Ah)
MSB
BIT 7
UIP
BIT 6
DV2
BIT 5
DV1
BIT 4
DV0
Bit 7: Update In Progress (UIP). This bit is a status flag
that can be monitored. When the UIP bit is 1, the update
transfer will soon occur. When UIP is 0, the update trans-
fer does not occur for at least 244μs. The time, calendar,
and alarm information in RAM is fully available for access
when the UIP bit is 0. The UIP bit is read-only. Writing the
SET bit in Register B to 1 inhibits any update transfer and
clears the UIP status bit.
BIT 3
RS3
BIT 2
RS2
BIT 1
RS1
LSB
BIT 0
RS0
Bits 6, 5, and 4: DV2, DV1, and DV0. These bits are
used to turn the oscillator on or off and to reset the count-
down chain. A pattern of 01X is the only combination of
bits that turns the oscillator on and allows the RTC to keep
time. A pattern of 11X enables the oscillator but holds
the countdown chain in reset. The next update occurs at
500ms after a pattern of 01X is written to DV0, DV1, and
DV2. DV0 is used to select bank 0 or bank 1 as defined in
Table 5. When DV0 is set to 0, bank 0 is selected. When
DV0 is set to 1, bank 1 is selected.
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