DS1744WP-120 查看數據表（PDF） - Unspecified
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DS1744WP-120 Datasheet PDF : 19 Pages
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
ORDERING INFORMATION
PART
VOLTAGE (V)
DS1744-70
5.0
DS1744-70+
5.0
DS1744-70IND
5.0
DS1744-100+
5.0
DS1744W-120
3.3
DS1744W-120+
3.3
DS1744W-120IND 3.3
DS1744P-70
5.0
DS1744P-70+
5.0
DS1744P-70IND
5.0
DS1744P-100+
5.0
DS1744WP-120
3.3
DS1744WP-120+
3.3
DS1744WP-120IND 3.3
TEMP RANGE
0℃ to +70℃
0℃ to +70℃
-40℃ to +85℃
0℃ to +70℃
0℃ to +70℃
0℃ to +70℃
-40℃ to +85℃
0℃ to +70℃
0℃ to +70℃
-40℃ to +85℃
0℃ to +70℃
0℃ to +70℃
0℃ to +70℃
-40℃ to +85℃
PIN-PACKAGE
28 EDIP
28 EDIP
28 EDIP
28 EDIP
28 EDIP
28 EDIP
28 EDIP
34 PowerCap*
34 PowerCap*
34 PowerCap*
34 PowerCap*
34 PowerCap*
34 PowerCap*
34 PowerCap*
TOP MARK**
DS1744-70
DS1744+70
DS1744-70IND
DS1744 +100
DS1744W -120
DS1744W +120
DS1744W -120IND
DS1744P-70
DS1744P+70
DS1744P-70IND
DS1744P+100
DS1744WP-120
DS1744WP+120
DS1744WP-120IND
+Denotes a lead-free/RoHS-complient device.
* DS9034-PCX, DS90341-PCX, DS9034-PCX + required (must be ordered separatedly).
** A “+” anywhere in the top mark denotes a lead-free device. An “IND” denotes an industrial temperature grade device.
DESCRIPTION
The DS1744 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 32k x 8 NV SRAM. User access
to all registers within the DS1744 is accomplished with a byte-wide interface as shown in Figure 1. The RTC information and
control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year are made automatically.
The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The
double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data.
The DS1744 also contains its own power-fail circuitry that deselects the device when the VCC supply is in an out-of-tolerance
condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and
update cycles are avoided.
Figure 1. Block Diagram
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