DS1744P-70 查看數據表（PDF） - Unspecified
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DS1744P-70 Datasheet PDF : 19 Pages
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DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is
running, the LSB of the seconds register toggles at 512Hz. When the seconds register is being read, the DQ0 line toggles at the
512Hz frequency as long as conditions for access remain valid (i.e.,
low, low, high, and address for seconds
register remain valid and stable).
CLOCK ACCURACY (DIP MODULE)
The DS1744 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The RTC is calibrated at the factory by
ARTSCHIP Semiconductor using nonvolatile tuning elements, and does not require additional calibration. For this reason,
methods of field clock calibration are not available and not necessary. Clock accuracy is also affected by the electrical
environment; caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional
information, refer to
Application Note 58: Crystal Considerations with ARTSCHIP Real-Time Clocks.
CLOCK ACCURACY (PowerCap MODULE)
The DS1744 and DS9034PCX are individually tested for accuracy. Once mounted together, the module typically keeps time
accuracy to within ±1.53 minutes per month (35ppm) at +25°C. Clock accuracy is also affected by the electrical environment and
caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional information, refer
to Application Note 58: Crystal Considerations with ARTSCHIP Real-Time Clocks.
Table 2. Register Map
ADDRESS
DATA
B7
B6
B5
B4
B3
7FFF
10 Year
7FFE
X
X
X
10 Month
7FFD
X
X
10 Date
7FFC
BF
FT
X
X
X
7FFB
X
X
10 Hour
7FFA
X
10 Minutes
7FF9
OSC
10 Seconds
7FF8
W
R
10 Century
B2
B1
Year
Month
Date
Day
Hour
Minutes
Seconds
Century
FUNCTION RANGE
B0
Year
00-99
Month
01-12
Date
01-31
Day
01-07
Hour
00-23
Minutes 00-59
Seconds 00-59
Century 00-39
= Stop Bit
R=Read Bit
FT=Frequency Test
W=Write Bit
X=See Note
BF=Battery Flag
Note: All indicated “X” bits are not used but must be set to a “0” during write cycle to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1744 is in the read mode whenever (output enable) is low, (write enable) is high, and
(chip enable) is low.
The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data is available at
the DQ pins within tAA after the last address input is stable, providing that the
and access times and states are satisfied.
If
or access times and states are not met, valid data is available at the latter of chip-enable access (tCEA) or at
output-enable access time (tOEA). The state of the DQ pins is controlled by
and . If the outputs are activated before tAA,
the data lines are driven to an intermediate state until tAA. If the address inputs are changed while
and remain valid,
output data remains valid for output-data hold time (tOH) but then goes indeterminate until the next address access.
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