DS1746WP-120IND 查看數據表（PDF） - Maxim Integrated

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DS1746WP-120IND

Y2K-Compliant, Nonvolatile Timekeeping RAMs

Maxim Integrated 

DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs

Table 1. Truth Table

VCC

CE OE WE

VCC>VPF

VSO<VCC<VPF

VCC<VSO<VPF

VIH X

X

VIL

X

VIL

VIL VIL VIH

VIL VIH VIH

XXX

XXX

MODE

Deselect

Write

Read

Read

Deselect

Deselect

DQ

High-Z

Data In

Data Out

High-Z

High-Z

High-Z

POWER

Standby

Active

Active

Active

CMOS Standby

Data-Retention Mode

SETTING THE CLOCK

As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates

to the device registers. The user can subsequently load correct date and time values into all eight registers,

followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new settings

into the clock, allowing timekeeping operations to resume from the new set point.

Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1 halts

updates to the device registers. The user can subsequently read the date and time values from the eight

registers without those contents possibly changing during those I/O operations. A subsequent write cycle

of 00h to the Control register to clear the R bit allows timekeeping operations to resume from the

previous set point.

The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified by a

write cycle to Control if either the W or R bits are being set to 1 in that write operation.

The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a write

cycle to Control if the W bit is being cleared to 0 in that write operation.

The pre-existing contents of the Control register bits 0:5 (Century value) will not be modified by a write

cycle to Control if the R bit is being cleared to 0 in that write operation.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off

to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers (see

Table 2). Setting it to a one stops the oscillator.

FREQUENCY TEST BIT

As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to

logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the

seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for

access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and

stable).

CLOCK ACCURACY (DIP MODULE)

The DS1746 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is

calibrated at the factory by Maxim using nonvolatile tuning elements, and does not require additional

calibration. For this reason, methods of field clock calibration are not available and not necessary. The

electrical environment also affects clock accuracy and caution should be taken to place the RTC in the

lowest-level EMI section of the PC board layout. For additional information, refer to Application Note

58.

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