ISL62881 查看數據表（PDF） - Renesas Electronics

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ISL62881

Single-Phase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs

Renesas Electronics 

ISL62881, ISL62881B

Diode Emulation and Period Stretching

PHASE

UGATE

LGATE

IL

FIGURE 8. DIODE EMULATION

ISL62881 can operate in diode emulation (DE) mode to improve

light load efficiency. In DE mode, the low-side MOSFET conducts

when the current is flowing from source to drain and doesn’t not

allow reverse current, emulating a diode. As shown in Figure 8,

when LGATE is on, the low-side MOSFET carries current, creating

negative voltage on the phase node due to the voltage drop

across the ON-resistance. The ISL62881 monitors the current

through monitoring the phase node voltage. It turns off LGATE

when the phase node voltage reaches zero to prevent the

inductor current from reversing the direction and creating

unnecessary power loss.

If the load current is light enough, as Figure 9 shows, the inductor

current will reach and stay at zero before the next phase node

pulse, and the regulator is in discontinuous conduction mode

(DCM). If the load current is heavy enough, the inductor current

will never reach 0A, and the regulator is in CCM although the

controller is in DE mode.

VCRS

CCM/DCM BOUNDARY

VW

IL

VCRS

VW LIGHT DCM

window size, therefore is the same, making the inductor current

triangle the same in the three cases. The ISL62881 clamps the

ripple capacitor voltage Vcrs in DE mode to make it mimic the

inductor current. It takes the COMP voltage longer to hit Vcrs,

naturally stretching the switching period. The inductor current

triangles move further apart from each other such that the inductor

current average value is equal to the load current. The reduced

switching frequency helps increase light load efficiency.

Start-up Timing

With the controller's VDD voltage above the POR threshold, the

start-up sequence begins when VR_ON exceeds the 3.3V logic

high threshold.

Figure 10 shows the typical start-up timing when the ISL62881 is

configured for CPU VR application. The ISL62881 uses digital

soft-start to ramp up DAC to the boot voltage of 1.1V at about

2.5mV/µs. Once the output voltage is within 10% of the boot voltage

for 13 PWM cycles (43µs for frequency = 300kHz), CLK_EN# is

pulled low and DAC slews at 5mV/µs to the voltage set by the VID

pins. PGOOD is asserted high in approximately 7ms. Similar results

occur if VR_ON is tied to VDD, with the soft-start sequence starting

120µs after VDD crosses the POR threshold.

Figure 11 shows the typical start-up timing when the ISL62881 is

configured for GPU VR application. The ISL62881 uses digital

soft-start to ramp-up DAC to the voltage set by the VID pins at

5mV/µs. Once the output voltage is within 10% of the target voltage

for 13 PWM cycles (43µs for frequency = 300kHz), CLK_EN# is

pulled low. PGOOD is asserted high in approximately 7ms. Similar

results occur if VR_ON is tied to VDD, with the soft-start sequence

starting 120µs after VDD crosses the POR threshold.

VDD

VR_ON

DAC

5mV/µs

2.5mV/µs

90%VBOOT

800µs

VID

COMMAND

VOLTAGE

13 SWITCHING CYCLES

CLK_EN#

PGOOD

~7ms

FIGURE 10. SOFT-START WAVEFORMS FOR CPU VR APPLICATION

IL

VCRS

DEEP DCM

VW

IL

FIGURE 9. PERIOD STRETCHING

Figure 9 shows the operation principle in diode emulation mode at

light load. The load gets incrementally lighter in the three cases

from top to bottom. The PWM on-time is determined by the VW

FN6924 Rev 3.00

June 16, 2011

VDD

VR_ON

DAC

5mV/µs

90%

120µs

VID COMMAND VOLTAGE

13 SWITCHING CYCLES

CLK_EN#

PGOOD

~7ms

FIGURE 11. SOFT-START WAVEFORMS FOR GPU VR APPLICATION

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