ISL62882HRTZ 查看數據表（PDF） - Renesas Electronics
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ISL62882HRTZ Datasheet PDF : 41 Pages
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ISL62882, ISL62882B
Functional Pin Descriptions (Continued)
ISL62882
13
14, 15
16
17
18
19
ISL62882B
16
17, 18
19
20
22
24
20
25
21
26
22
27
23
28
24
29
-
-
25
30
26
32
27
33
28
34
29
35
30
36
31 thru 37
38
39
38 thru 44
45
46
40
47
-
48
pad
pad
SYMBOL
RTN
ISUM- and ISUM+
VDD
VIN
IMON
BOOT1
UGATE1
PHASE1
VSSP1
LGATE1a
LGATE1b
LGATE1
VCCP
LGATE2
VSSP2
PHASE2
UGATE2
BOOT2
VID0 thru VID6
VR_ON
DPRSLPVR
CLK_EN#
NC
BOTTOM
DESCRIPTION
Remote voltage sensing return. Connect to ground at microprocessor die.
Droop current sense input.
5V bias power.
Battery supply voltage, used for feed-forward.
An analog output. IMON outputs a current proportional to the regulator output current.
Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is
charged through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each
time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot
diode.
Output of the Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the
Phase-1 high-side MOSFET.
Current return path for the Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-1.
Current return path for the Phase-1 low-side MOSFET gate driver. Connect the VSSP1 pin to the
source of the Phase-1 low-side MOSFET through a low impedance path, preferably in parallel
with the traces connecting the LGATE1a and the LGATE1b pins to the gates of the Phase-1
low-side MOSFETs.
Output of the Phase-1 low-side MOSFET gate driver that is always active. Connect the LGATE1a
pin to the gate of the Phase-1 low-side MOSFET that is active all the time.
Another output of the Phase-1 low-side MOSFET gate driver. This gate driver will be pulled low
when the DPRSLPVR pin logic is high. Connect the LGATE1b pin to the gate of the Phase-1
low-side MOSFET that is idle in deeper sleep mode.
Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the
Phase-1 low-side MOSFET.
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at
least 1µF of an MLCC capacitor to VSSP1 and VSSP2 pins respectively.
Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of the
Phase-2 low-side MOSFET.
Current return path for the Phase-2 converter low-side MOSFET gate driver. Connect the VSSP2
pin to the source of the Phase-2 low-side MOSFET through a low impedance path, preferably in
parallel with the trace connecting the LGATE2 pin to the gate of the Phase-2 low-side MOSFET.
Current return path for the Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-2.
Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of the
Phase-2 high-side MOSFET.
Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is
charged through an internal boot diode connected from the VCCP pin to the BOOT2 pin, each
time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot
diode.
VID input with VID0 = LSB and VID6 = MSB.
Voltage regulator enable input. A high level logic signal on this pin enables the regulator.
Deeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessor
is in deeper sleep mode.
Open drain output to enable system PLL clock. It goes low 13 switching cycles after Vcore is
within 10% of Vboot.
No connect.
The bottom pad of ISL62882B is electrically connected to the GND pin inside the IC.
FN6890 Rev 4.00
June 21, 2011
Page 3 of 41
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